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| Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY 7549 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION The 7549 Group is the 8-bit microcomputer based on the 740 family core technology. The 7549 Group has an 8-bit timer, 16-bit timer, serial interface, A/D converter, power-on reset circuit and the low voltage detection circuit. Also, the Function set ROM is equipped. FEATURES * Basic machine-language instructions ..................................71 * The minimum instruction execution time ................... 0.25 s (at 8 MHz oscillation frequency, double-speed mode) * Memory size ROM ................................... 2 K, 4K, 6 K bytes RAM ........................................... 192/256 bytes * Programmable I/O ports I/O port............................................................19 Output port........................................................1 * Key-on wakeup .......................................................................8 * LED direct drive port..............................................................8 * Interrupts ............................................. 13 sources, 13 vectors * Timers ....................................................................... 8-bit x 2 ..................................................................................16-bit x 1 * Output compare ........................................................ 3 channel * Input capture ............................................................. 1 channel REJ03B0202-0200 Rev.2.00 Mar 05, 2007 * Serial interface............................................................ 8-bit x 1 (UART or clock synchronous) * A/D converter ............................ 10-bit resolution x 8-channel * Clock generating circuit ..................................... Built-in type (connect to external ceramic resonator or quartz-crystal oscillator, 32 kHz quartz-crystal oscillation available) * High-speed on-chip oscillator ............................ Typ. : 4 MHz * Low-speed on-chip oscillator .......................... Typ. : 250 kHz * Watchdog timer ...................................................... 16-bit x 1 * Power-on reset circuit.......................................... Built-in type * Low voltage detection circuit .............................. Built-in type * Power source voltage XIN oscillation frequency (at ceramic resonator, in double-speed mode) At 8 MHz ........................................ 4.5 to 5.5 V At 2 MHz ........................................ 2.4 to 5.5 V At 1 MHz ........................................ 2.2 to 5.5 V XIN oscillation frequency (at ceramic resonator, in high-speed mode) At 8 MHz ........................................ 4.0 to 5.5 V At 4 MHz ........................................ 2.4 to 5.5 V At 1 MHz ........................................ 1.8 to 5.5 V High-speed on-chip oscillator oscillation frequency At 4 MHz......................................... 4.0 to 5.5 V Low-speed on-chip oscillator oscillation frequency At 250 kHz (typ. value at VCC = 5V).... 1.8 to 5.5 V * Power dissipation ........................................................ 30 mW * Operating temperature range ............................... -20 to 85C APPLICATION Office automation equipment, factory automation equipment, home electric appliances, consumer electronics, etc. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 1 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY PIN Configuration (top view) P14/AN4/KEY4 P15/AN5/KEY5 RESET P16/AN6/KEY6 P17/AN7/KEY7 P20/XOUT/XCOUT VSS P21/XIN/XCIN VCC CNVSS P00(LED0)/INT0 P01(LED1)/INT1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P31 P30 P07(LED7)/SRDY P06(LED6)/SCLK P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) Package type: PRSP0024GA-A (24P2Q-A) Fig 1. Pin configuration (PRSP0024GA-A type) M37549G3/G2/G1FP Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 2 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY PIN Configuration (top view) NC NC NC P14/AN4/KEY4 P15/AN5/KEY5 RESET P16/AN6/KEY6 P17/AN7/KEY7 NC NC NC P20/XOUT/XCOUT VSS P21/XIN/XCIN VCC CNVSS P00(LED0)/INT0 P01(LED1)/INT1 NC NC VSS NC NC P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P31 P30 NC NC NC NC P07(LED7)/SRDY P06(LED6)/SCLK P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) NC NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 Package type: 42S1M Fig 2. Pin configuration (42S1M type) M37549RLSS Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 3 of 70 7549 Group PERFORMANCE OVERVIEW Table 1 Performance overview Parameter Number of basic instructions Instruction execution time Oscillation frequency Memory sizes ROM M37549G1 M37549G2 M37549G3 RAM M37549G1 M37549G2 M37549G3 I/O port P00-P07 I/O P10-P17 I/O P20 P21 Interrupt Timer Output compare Input capture Serial interface A/D converter Watchdog timer Power-on reset circuit Low voltage detection circuit Clock generating circuit Function set ROM area Function set ROM Source Output I/O 71 Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Function 0.25 s (Minimum instruction, oscillation frequency 8MHz, double-speed mode) 8 MHz (Maximum) 2K bytes x 8 bits 4K bytes x 8 bits 6K bytes x 8 bits 192 bytes x 8 bits 256 bytes x 8 bits 256 bytes x 8 bits 1-bit x 8, LED direct drive ports 1-bit x 8 1-bit x 1 1-bit x 1 1-bit x 2 13 sources, 13 vectors 8-bit x 2, 16-bit x 1 3-channel 1 channel 8-bit x 1 (UART or clock synchronous) 10-bit resolution x 8 channel 16-bit x 1 Built-in Built-in Built-in (external ceramic resonator or quartz-crystal oscillator, external 32-kHz quartz-crystal oscillator available) (built-in high/low-speed on-chip oscillator) Function set ROM is assigned to address FFD816 to FFDA16. Valid/invaid of low voltage detection circuit can be selected. Oscillation mode can be selected. Enable/disable of watchdog timer and STP instruction can be selected. ROM code protect is assigned to address FFDB16. Read/write the built-in QzROM by serial programmer is disabled by setting "00" to ROM code protect. 4.5 to 5.5 V 2.4 to 5.5 V 2.2 to 5.5 V 4.0 to 5.5 V 2.4 to 5.5 V 1.8 to 5.5 V 4.0 to 5.5 V P30, P31 I/O ROM code protect Power source voltage (at ceramic resonator) Double- at 8 MHz oscillation speed at 2 MHz oscillation mode at 1 MHz oscillation Highspeed mode at 8 MHz oscillation at 4 MHz oscillation at 1 MHz oscillation Power source voltage (at high-speed onchip oscillator) Power source voltage (at low-speed onchip oscillator) Power dissipation Double- at 4 MHz oscillation speed mode Double- at 250 kHz oscillation speed mode 1.8 to 5.5 V TBD -20 to 85 C CMOS sillicon gate 24-pin plastic molded SSOP (PRSP0024GA-A) 42-pin shrink ceramic PIGGY BACK (42S1M) Operating temperature range Device structure Package Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 4 of 70 7549 Group Fig 3. VSS VCC 9 10 3 7 FUNCTIONAL BLOCK DIAGRAM Reset input RESET CNVSS Rev.2.00 Mar 05, 2007 REJ03B0202-0200 CPU RAM A Prescaler 12 (8) X Y S PCH PS PCL Timer A(16) ROM Timer 1(8) FUNCTIONAL BLOCK DIAGRAM Timer 2 (8) Power-on reset circuit Reset Page 5 of 70 0 Low voltage detection circuit Reset Watchdog timer Reset 0 Clock generating circuit A/D converter (10) Compare (16) SIO (8) Capture (16) INT0 PRELIMINARY P3(2) P2(2) P1(8) Key-on wakeup P0(8) INT1 20 19 86 5 4 2 1 24 23 22 21 18 17 16 15 14 13 12 11 I/O port P3 I/O port P2 Notice: This is not a final specification. Some parametric limits are subject to change. Clock input Clock output XIN/XCIN XOUT/XCOUT I/O port P1 I/O port P0 7549 Group PIN DESCRIPTION Table 2 Pin description Pin VCC,VSS CNVSS RESET P00(LED0)/INT0 P01(LED1)/INT1 P02(LED2) P03(LED3)/CAP0 P04(LED4)/RXD P05(LED5)/TXD P06(LED6)/SCLK P07(LED7)/SRDY P10/AN0/KEY0/CMP0 P11/AN1/KEY1/CMP1 P12/AN2/KEY2/CMP2 P13/AN3/KEY3/T2OUT I/O port P1 Name Power source CNVSS Reset input I/O port P0 Function Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Function expect a port function Apply voltage of 1.8 to 5.5 V to Vcc, and 0 V to Vss. Controls the operation mode of the chip. Connected to VSS. Reset input pin for active "L" Interrupt input pin *8-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. Capture input pin *CMOS compatible input level *CMOS 3-state output structure Serial interface function pin *Whether a built-in pull-up resistor is to be used or not can be determined by program. *High drive capacity for LED drive port can be selected by program. Input pins *8-bit I/O port. *I/O direction register allows each pin to be individu- for A/D converter ally programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *Whether a built-in pull-up resistor is to be used or not can be determined by program. Key-input (key-on wake up interrupt input) pin Compare output pin Timer 2 output pin P14/AN4/KEY4 P15/AN5/KEY5 P16/AN6/KEY6 P17/AN7/KEY7 P20/XOUT/XCOUT P21/XIN/XCIN (Note) I/O port P2 *2-bit I/O port. (P20/XOUT/XCOUT is only for output) *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure *Function set ROM allows pins to be used as clock pins. Pins XIN and XOUT, or pins XCIN and XCOUT, can be used as clock pins by connecting a ceramic resonator, crystal oscillator, or 32 kHz crystal oscillator between them. Alternately, an external clock may be input to the P20/XOUT/XCOUT pin. In this case, the P21/XIN/XCIN pin can be used as an I/O port. P30, P31 I/O port P3 *2-bit I/O port. *I/O direction register allows each pin to be individually programmed as either input or output. *CMOS compatible input level *CMOS 3-state output structure NOTE: 1. The oscillation circuit is built in the P20/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer is lower than the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is connected and undefined values may be output from these pins. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 6 of 70 7549 Group GROUP EXPANSION Renesas plans to expand the 7549 group as follow: Memory Type Support for QzROM version and emulator MCU. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Memory Size * ROM size ...................................................... 2 K to 6 K bytes * RAM size ..................................................... 192 to 256 bytes Packages * PRSP0024GA-A .... 0.8 mm-pitch 24-pin plastic molded SSOP * 42S1M ......................... 42-pin shrink ceramic PIGGY BACK RO M size (bytes) 6K M 37549G 3 ** 4K M 37549G 2 ** 2K M 37549G1 ** 0 192 256 RAM size (bytes) **: Under developm ent Note: Products under developm ent***the developm ent schedule and specification m ay be revised without notice. Fig 4. Memory expansion plan Currently supported products are listed below. Table 3 List of supported products Part number M37549G3-XXXFP M37549G3FP M37549G2-XXXFP M37549G2FP M37549G1-XXXFP M37549G1FP M37549RLSS NOTE: ROM size (bytes) ROM size for User () 6144 (6014) 4096 (3966) 2048 (1918) - RAM size (bytes) 256 256 192 256 Package PRSP0024GA-A PRSP0024GA-A PRSP0024GA-A 42S1M Remarks QzROM version QzROM version (blank) QzROM version QzROM version (blank) QzROM version QzROM version (blank) Emulator MCU 1. ROM size includes the function set ROM. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 7 of 70 7549 Group FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The MCU uses the standard 740 family instruction set. Refer to the table of 740 family addressing modes and machine-language instructions or the SERIES 740 Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. The stack is used to store the current address data and processor status when branching to subroutines or interrupt routines. The lower eight bits of the stack address are determined by the contents of the stack pointer. The upper eight bits of the stack address are determined by the Stack Page Selection Bit. If the Stack Page Selection Bit is "0", then the RAM in the zero page is used as the stack area. If the Stack Page Selection Bit is "1", then RAM in page 1 is used as the stack area. The Stack Page Selection Bit is located in the SFR area in the zero page. Note that the initial value of the Stack Page Selection Bit varies with each microcomput er type. Al so some microcomputer types have no Stack Page Selection Bit and the upper eight bits of the stack address are fixed. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PCH and PCL. It is used to indicate the address of the next instruction to be executed. b7 A b7 X b7 Y b7 S b15 PCH b7 PCL b0 Accumulator b0 Index Register X b0 Index Register Y b0 Stack Pointer b0 Program Counter b7 b0 N V T B D I Z C Processor Status Register (PS) Carry Flag Zero Flag Interrupt Disable Flag Decimal Mode Flag Break Flag Index X Mode Flag Overflow Flag Negative Flag Fig 5. 740 Family CPU register structure Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 8 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY On-going Routine Interrupt request (Note) M(S)(PCH) (S)(S) - 1 Execute JSR M(S)(PCL) Store Return Address on Stack Store Return Address on Stack M(S)(PCH) (S)(S) - 1 M(S)(PCL) (S)(S) - 1 (S)(S) - 1 M(S)(PS) (S)(S) - 1 Interrupt Service Routine ..... Store Contents of Processor Status Register on Stack Subroutine ..... I Flag "0" to "1" Fetch the Jump Vector Execute RTI (S)(S) + 1 (PS)M(S) (S)(S) + 1 (PCL)M(S) (S)(S) + 1 (PCH)M(S) Execute RTS (S)(S) + 1 (PCL)M(S) (S)(S) + 1 (PCH)M(S) Restore Return Address Restore Contents of Processor Status Register Restore Return Address Note : The condition to enable the interrupt Interrupt enable bit is "1" Interrupt disable flag is "0" Fig 6. Table 4 Register push and pop at interrupt generation and subroutine call Push and pop instructions of accumulator or processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Accumulator Processor status register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 9 of 70 7549 Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of flags which indicate the status of the processor after an arithmetic operation. Branch operations can be performed by testing the Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid. After reset, the Interrupt disable (I) flag is set to "1", but all other flags are undefined. Since the Index X mode (T) and Decimal mode (D) flags directly affect arithmetic operations, they should be initialized in the beginning of a program. Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction. Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is "0", and cleared if the result is anything other than "0". Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is "1". When an interrupt occurs, this flag is automatically set to "1" to prevent other interrupts from interfering until the current interrupt is serviced. Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is "0"; decimal arithmetic is executed when it is "1". Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic. Table 5 Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was generated by the BRK instruction. The BRK flag in the processor status register is always "0". When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to "1". The saved processor status is the only place where the break flag is ever set. Bit 5: Index X mode flag (T) When the T flag is "0", arithmetic operations are performed between accumulator and memory, e.g. the results of an operation between two memory locations is stored in the accumulator. When the T flag is "1", direct arithmetic operations and direct data transfers are enabled between memory locations, i.e. between memory and memory, memory and I/O, and I/O and I/O. In this case, the result of an arithmetic operation performed on data in memory location 1 and memory location 2 is stored in memory location 1. The address of memory location 1 is specified by index register X, and the address of memory location 2 is specified by normal addressing modes. Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to 128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag. Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Set and clear instructions of each bit of processor status register C flag SEC CLC Z flag - - I flag SEI CLI D flag SED CLD B flag - - T flag SET CLT V flag - CLV N flag - - Set instruction Clear instruction [CPU mode register] CPUM The CPU mode register contains the stack page selection bit. This register is allocated at address 003B16. b7 b0 CPU mode register (CPUM: address 003B16, initial value: 0016) Processor mode bits b1b0 0 0: 0 1: 1 0: 1 1: Single-chip mode Not available Not available Not available Stack page selection bit 0 : 0 page 1 : 1 page Disable (returns "0" when read) Fig 7. Structure of CPU mode register The processor mode bits can be written only once after releasing reset. Always set them to "002". After written, rewriting any data to these bits is disabled because they are locked. (Emulator MCU is excluded.) Also, the stack page bit (bit 2) is not locked. In order to prevent error-writing to the processor mode bits (at program runaway), write the CPU mode register at the start of the program that runs after releasing reset. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 10 of 70 7549 Group Memory * Special Function Register (SFR) Area The SFR area in the zero page contains control registers such as I/O ports and timers. * RAM RAM is used for data storage and for a stack area of subroutine calls and interrupts. * ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is a user area for storing programs. The user area includes the function set ROM area. * Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. * Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function registers (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. * Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Access to this area with only 2 bytes is possible in the special page addressing mode. * Function set ROM Area [Renesas shipment test area] Figure 8 shows the Assignment of Function set ROM area. The random data are set to the Renesas shipment test areas (addresses FFD416 to address FFD716). Do not rewrite the data of these areas. When the checksum is included in the user program, avoid assigning it to these areas. [Function set ROM data] FSROM0, FSROM1, FSROM2 Function set ROM data 0 to 2 (addresses FFD816 to FFDA16) are used to set modes of peripheral functions. By setting values to these areas, the operation mode of each peripheral function are set after releasing reset. Refer to the descriptions of peripheral functions for the details of operation of peripheral functions. * Clock circuit * Watchdog timer * Low voltage detection circuit Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY [ROM code protect] Address FFDB16 of QzROM version is ROM code protect address and cannot be used for programming. "0016" is written into this address when selecting the protect bit write by using a serial programmer and selecting protect enabled for writing shipment by Renesas Technology corp.. When "0016" is set to the ROM code protect address, the protect func-tion is enabled, so that reading or writing from/to the corresponding area is disabled by a serial programmer. As for the QzROM product in blank, the ROM code is protected by selecting the protect bit write at ROM writing with a serial programmer. As for the QzROM product shipped after writing, "0016" (protect enabled) or "FF16" (protect disabled) is written into the ROM code protect address when Renesas Technology corp. performs writing. The writing of "0016" or "FF16" can be selected as ROM option setup ("MASK option" written in the mask file converter) when ordering. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 11 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY User ROM area RAM area RAM capacity (bytes) 192 256 000016 address XXXX16 00FF16 013F16 RAM SFR area 004016 010016 Zero page ROM area ROM capacity (K bytes) 2 4 6 Function set ROM Address FFD416 FFD516 FFD616 FFD716 FFD816 FFD916 FFDA16 FFDB16 Renesas shipment test area Renesas shipment test area Renesas shipment test area Renesas shipment test area Function set ROM data 0 Function set ROM data 1 Function set ROM data 2 ROM code protect address YYYY16 F80016 F00016 E80016 address ZZZZ16 F88016 F08016 E88016 XXXX16 Reserved area 044016 Disable YYYY16 Reserved ROM area (128 bytes) ZZZZ16 ROM FF0016 FFD416 FFDC16 Interrupt vector area FFFE16 FFFF16 Reserved ROM area Function set ROM area Special page Fig 8. Memory map diagram Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 12 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY 000016 Port P0 (P0) 000116 Port P0 direction register (P0D) 000216 Port P1 (P1) 000316 Port P1 direction register (P1D) 000416 Port P2 (P2) 000516 Port P2 direction register (P2D) 000616 Port P3 (P3) 000716 Port P3 direction register (P3D) 000816 Reserved 000916 Reserved 000A16 Reserved 000B16 Reserved 000C16 Port P0 drive capacity control register (DCCR) 000D16 Port P0 pull-up control register (PULL0) 000E16 Port P1 pull-up control register (PULL1) 000F16 Key-on wakeup input selection register (KEYS) 001016 Capture/Compare register (low-order) (CRAL) 001116 Capture/Compare register (high-order) (CRAH) 001216 Capture/Compare register R/W pointer (CCRP) 001316 Compare output mode register (CMOM) 001416 Timer A (low-order) (TAL) 001516 Timer A (high-order) (TAH) 001616 Reserved 001716 Reserved 001816 Transmit/Receive buffer register (TB/RB) 001916 Serial I/O status register (SIOSTS) 001A16 Serial I/O control register (SIOCON) 001B16 UART control register (UARTCON) 001C16 Baud rate generator (BRG) 001D16 Reserved 001E16 Reserved 001F16 Reserved 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer mode register (TM) 002C16 Timer count source set register (TCSS) 002D16 Compare register re-load register (CMPR) 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 Capture/Compare port register (CCPR) Capture/Compare status register (CCSR) Compare interrupt source set register (CISR) Capture software trigger register (CSTR) Capture mode register (CAPM) Reserved AD control register (ADCON) AD conversion register (low-order) (ADL) AD conversion register (high-order) (ADH) Clock mode register (CLKM) Oscillation stop detection register (CLKSTP) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) 003C16 Interrupt request register 1 (IREQ1) 003D16 Interrupt request register 2 (IREQ2) 003E16 003F16 Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) Note 1: Do not access to the reserved addresses. Fig 9. Memory map of special function register (SFR) Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 13 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Function set ROM data 0 (FSROM0: address FFD816) Low voltage detection circuit valid bit 0: Low voltage detection circuit invalid 1: Low voltage detection circuit valid Set "0" to this bit certainly. Set "1" to this bit certainly. Fig 10. Structure of Function set ROM data 0 b7 b0 Function set ROM data 1 FSROM1 (FFD916) Oscillation method selection bits (Note 1) b1 b0 0 0: Clock pins not used (P20/XOUT and P21/XIN are used as I/O ports) 0 1: Ceramic resonator or quarts-crystal oscillator 1 0: 32 kHz quarts-crystal oscillator 1 1: External clock input (P21/XIN pin is used as I/O port) Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set "0" to these bits certainly. Set "1" to this bit certainly. Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used as I/O ports, the oscillator circuit is enabled when the MCU's Vcc voltage drops below the operation limit voltage. In this case these pins may output undefined values. 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. Fig 11. Structure of Function set ROM data 1 b7 b0 Function set ROM data 2 FSROM2 (FFDA16) Watchdog timer source clock selection bit 0 : Low-speed on-chip oscillator/16 1 : System clock/16 Watchdog timer start selection bit 0 : Start watchdog timer 1 : Stop watchdog timer Watchdog timer H count source initial value selection bit 0 : Initial value of bit 7 of WDTCON after reset release is "0" 1 : Initial value of bit 7 of WDTCON after reset release is "1" STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Low-speed on-chip oscillator control bit (Note 1) 0 : Stop of low-speed on-chip oscillator disabled 1 : Stop of low-speed on-chip oscillator enabled Set "0" to these bits certainly. Note 1: If "0" is set to this bit, it is not possible to write "1" to bit 0 in the clock mode register. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed. Fig 12. Structure of Function set ROM data 2 Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 14 of 70 7549 Group I/O Ports [Direction registers] PiD The I/O ports have direction registers which determine the input/ output direction of each pin. Each bit in a direction register corresponds to one pin, and each pin can be set to be input or output. When "1" is set to the bit corresponding to a pin, this pin becomes an output port. When "0" is set to the bit, the pin becomes an input port. When data is read from a pin set to output, not the value of the pin itself but the value of port latch is read. Pins set to input are floating, and permit reading pin values. If a pin set to input is written to, only the port latch is written to and the pin remains floating. If the port P20 is used as output port, write "1" to the port P20 direction register after reset. [Port P0 drive capacity control register] DCCR By setting the Port P0 drive capacity control register (address 000C16), the drive capacity of the N-channel output transistor for the port P0 can be selected. [Pull-up control registers] PULL0, PULL1 By setting the pull-up control registers (address 000D16 and 000E16), ports P0 and P1 can exert pull-up control by program. However, this is valid only when the port direction registers are set to input. When they are set to output, setting "pull-up on" does not pull up the ports. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Port P0 drive capacity control register (DCCR: address 000C16, initial value: 0016) Port P00 drive capacity selection bit Port P01 drive capacity selection bit Port P02 drive capacity selection bit Port P03 drive capacity selection bit Port P04 drive capacity selection bit Port P05 drive capacity selection bit Port P06 drive capacity selection bit Port P07 drive capacity selection bit 0: weakness 1: strength Fig 13. Structure of port P0 drive capacity control register b7 b0 Port P0 pull-up control register (PULL0: address 000D16, initial value: 0016) P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit 0: Pull-up is disabled 1: Pull-up is enabled Fig 14. Structure of port P0 pull-up control register b7 b0 Port P1 pull-up control register (PULL1: address 000E16, initial value: 0016) P10 pull-up control bit P11 pull-up control bit P12 pull-up control bit P13 pull-up control bit P14 pull-up control bit P15 pull-up control bit P16 pull-up control bit P17 pull-up control bit 0: Pull-up is disabled 1: Pull-up is enabled Fig 15. Structure of port P1 control register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 15 of 70 7549 Group Table 6 Pin P00(LED0)/INT0 P01(LED1)/INT1 P02(LED2) P03(LED3)/CAP0 Capture input Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY I/O port function table Name I/O port P0 I/O format CMOS compatible input level CMOS 3-state output Non-port function External interrupt input SFRs related each pin Interrupt edge selection register Port P0 drive capacity control register Port P0 pull-up control register Port P0 drive capacity control register Port P0 pull-up control register Capture/Compare port register Port P0 drive capacity control register Port P0 pull-up control register Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register Serial I/O control register UART control register Port P0 drive capacity control register Port P0 pull-up control register Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register Serial I/O control register Port P0 drive capacity control register Port P0 pull-up control register I/O port P1 Compare output Key input interrupt A/D conversion input Timer 2 output Key input interrupt A/D conversion input Key input interrupt A/D conversion input Capture/Compare port register Port P1 pull-up control register Key-on wakeup input selection register AD control register Timer mode register Port P1 pull-up control register Key-on wakeup input selection register AD control register Port P1 pull-up control register Key-on wakeup input selection register AD control register Function set ROM data 1 (Note) Clock mode register Function set ROM data 1 (Note) Clock mode register P04(LED4)/RXD Serial interface input/ output P05(LED5)/TXD P06(LED6)/SCLK P07(LED7)/SRDY P10/AN0/KEY0/CMP0 P11/AN1/KEY1/ CMP1P12/AN2/KEY2/ CMP2 P13/AN3/KEY3/T2OUT P14/AN4/KEY4 P15/AN5/KEY5 P16/AN6/KEY6 P17/AN7/KEY7 P20/XOUT/XCOUT P21/XIN/XCIN P30 P31 I/O port P3 I/O port P2 CMOS 3-state output CMOS compatible input level CMOS 3-state output Clock pin Clock pin NOTE: 1. Function set ROM data 1 is included in the function set ROM area. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 16 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (1) Port P00 Pull-up control bit Direction register Data bus Port latch (2) Port P01 Pull-up control bit Direction register Data bus Port latch Drive capacity control bit INT0 input INT1 input Drive capacity control bit (3) Port P02 Pull-up control bit Direction register Data bus Port latch (4) Port P03 Pull-up control bit Direction register Data bus Port latch Drive capacity control bit CAP0 input Drive capacity control bit (5) Port P04 Pull-up control bit Serial I/O enable bit Receive enable bit Direction register Data bus Port latch (6) Port P05 P05/TXD P-channel output disable bit Serial I/O enable bit Transmit enable bit Direction register Data bus Port latch Pull-up control bit Drive capacity control bit Serial I/O input Serial I/O output Drive capacity control bit (7) Port P06 Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Direction register Data bus Port latch Pull-up control bit (8) Port P07 Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit Direction register Data bus Port latch Pull-up control bit Drive capacity control bit Serial I/O clock output Serial I/O clock input Note: Serial I/O ready output Drive capacity control bit represents a parasitic diode. No current flow is possible. Ensure that the input voltage to each pin does not exceed the absolute maximum rating. Fig 16. Block diagram of pins (1) Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 17 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (9) Port P10, P11, P12 Pull-up control bit Direction register Data bus Port latch (10) Port P13 Pull-up control bit Direction register Data bus Port latch Compare output Compare output port selection bit Key input interrupt A/D converter input Timer2 output P13/T2OUT output valid bit Key-on wakeup input selection bit Analog input pin selection bit Key input interrupt A/D converter input Key-on wakeup input selection bit Analog input pin selection bit (11) Port P14 - P17 Pull-up control bit Direction register Data bus Port latch (12) Port P20, P21 (Note) Pull-up control at STP P20/XOUT/XCOUT Direction register Data bus Port latch Clock input Key input interrupt A/D converter input Oscillation mode selection bit (function set ROM data 1) Key-on wakeup input selection bit Analog input pin selection bit P21/XIN/XCIN (13) Port P30, P31 Direction register Data bus Port latch Data bus Direction register Port latch Note: Set to "1" the port P20 direction register. (14) CNVss QzROM programming power supply Mode setting signal input (15) RESET Reset signal input Note: represents a parasitic diode. No current flow is possible. Ensure that the input voltage to each pin does not exceed the absolute maximum rating. Fig 17. Block diagram of pins (2) Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 18 of 70 7549 Group Termination of unused pins * Termination of common pins I/O ports: Select an input port or an output port and follow each processing method. Output ports: Open. Input ports: If the input level become unstable, through current flow to an input circuit, and the power supply current may increase. Especially, when expecting low consumption current (at STP or WIT instruction execution etc.), pull-up or pull-down input ports to prevent through current (built-in resistor can be used). We recommend processing unused pins through a resistor which can secure IOH (avg) or IOL (avg). Because, when an I/O port or a pin which have an output function is selected as an input port, it may operate as an output port by incorrect operation etc. Table 7 Termination of unused pins Pin P00/INT0 P01/INT1 P02 P03 P04/RXD P05/TXD P06/SCLK P07/SRDY P10/AN0/KEY0/CMP0 P11/AN1/KEY1/CMP1 P12/AN2/KEY2/CMP2 P13/AN3/KEY3/T2OUT P14/AN4/KEY4 P15/AN5/KEY5 P16/AN6/KEY6 P17/AN7/KEY7 P20/XOUT/XCOUT P21/XIN/XCIN P30 P31 Termination Perform termination of I/O port. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Set the direction register to "1", and perform termination of output port. Perform termination of I/O port. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 19 of 70 7549 Group Interrupts Interrupts occur by 13 different sources : 5 external sources, 7 internal sources and 1 software source. * Interrupt control All interrupts except the BRK instruction interrupt have an interrupt request bit and an interrupt enable bit, and they are controlled by the interrupt disable flag. When the interrupt enable bit and the interrupt request bit are set to "1" and the interrupt disable flag is set to "0", an interrupt is accepted. The interrupt request bit can be cleared by program but not be set. The interrupt enable bit can be set and cleared by program. The reset and BRK instruction interrupt can never be disabled with any flag or bit. All interrupts except these are disabled when the interrupt disable flag is set. When several interrupts occur at the same time, the interrupts are received according to priority. * Interrupt operation Upon acceptance of an interrupt the following operations are automatically performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status register are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. Concurrently with the push operation, the interrupt destination address is read from the vector table into the program counter. [Interrupt edge selection register] INTEDGE The valid edge of external interrupt INT0 and INT1 can be selected by the interrupt edge selection bit, respectively. [Key-on wakeup input selection register] KEYS Either of enable or disable of key-on wakeup for pins P10 to P17 can be selected by the key-on wakeup input selection bit, respectively. b7 b0 Key-on wakeup input selection register KEYS (000F16), initial value: 0016 Port P10 key-on wakeup input selection bit Port P11 key-on wakeup input selection bit Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY * Notes on use (1) When setting the followings, the interrupt request bit may be set to "1". * When switching external interrupt active edge related register: Interrupt edge selection register (address 003A16) Capture mode register (address 003216) When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. 1. Set the corresponding interrupt enable bit to "0" (disabled). 2. Set the interrupt edge select bit (active edge switch bit, trigger mode bit). 3. Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. 4. Set the corresponding interrupt enable bit to "1" (enabled). Port P12 key-on wakeup input selection bit Port P13 key-on wakeup input selection bit 0: Disable 1: Enable Port P14 key-on wakeup input selection bit Port P15 key-on wakeup input selection bit Port P16 key-on wakeup input selection bit Port P17 key-on wakeup input selection bit Fig 18. Structure of key-on wakeup input selection register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 20 of 70 7549 Group Table 8 Interrupt vector address and priority Priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 BRK instruction 17 Vector addresses (Note 1) Highorder FFFD16 FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFE716 FFE516 FFE316 FFE116 FFDF16 FFDD16 Loworder FFFC16 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 FFE616 FFE416 FFE216 FFE016 FFDE16 FFDC16 At BRK instruction execution Interrupt request generating conditions At reset input At completion of serial I/O data receive Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Interrupt source Reset (Note 2) Serial I/O receive Serial I/O transmit INT0 INT1 Key-on wakeup Capture Compare Timer A Timer 2 A/D conversion Timer 1 Not used Remarks Non-maskable Valid only when serial I/O is selected At completion of serial I/O transmit shift or Valid only when serial I/O is selected when transmit buffer is empty At detection of either rising or falling edge External interrupt of INT0 input (active edge selectable) At detection of either rising or falling edge External interrupt of INT1 input (active edge selectable) At falling of conjunction of input logical level for port P1 (at input) External interrupt (valid at falling edge) At detection of either rising or falling edge External interrupt of Capture 0 input (active edge selectable) At compare matched At timer A underflow At timer 2 underflow At completion of A/D conversion At timer 1 underflow STP release timer underflow Compare interrupt source is selected. Non-maskable software interrupt NOTES: 1. Vector addressed contain internal jump destination addresses. 2. Reset function in the same way as an interrupt with the highest priority. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 21 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Interrupt request bit Interrupt enable bit Interrupt disable flag I BRK instruction Reset Interrupt request Fig 19. Interrupt control b7 b0 Interrupt edge selection register (INTEDGE: address 003A16, initial value: 0016) INT0 interrupt edge selection bit 0: Falling edge active 1: Rising edge active INT1 interrupt edge selection bit 0: Falling edge active 1: Rising edge active Not used (returns "0" when read) b7 b0 Interrupt control register 1 (ICON1: address 003E16, initial value: 0016) Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit INT0 interrupt enable bit INT1 interrupt enable bit Key-on wake up interrupt enable bit Capture interrupt enable bit Compare interrupt enable bit Timer A interrupt enable bit 0: Interrupts disabled 1: Interrupts enabled b7 b0 Interrupt request register 1 (IREQ1: address 003C16, initial value: 0016) Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit INT0 interrupt request bit INT1 interrupt request bit Key-on wake up interrupt request bit Capture interrupt request bit Compare interrupt request bit Timer A interrupt request bit 0: No interrupt request issued 1: Interrupt request issued b7 b0 Interrupt control register 2 (ICON2: address 003F16, initial value: 0016) Timer 2 interrupt enable bit A/D conversion interrupt enable bit Timer 1 interrupt enable bit Not used (returns "0" when read) (Do not write "1" to this bit) 0: Interrupts disabled 1: Interrupts enabled b7 b0 Interrupt request register 2 (IREQ2: address 003D16, initial value: 0016) Timer 2 interrupt request bit A/D conversion interrupt request bit Timer 1 interrupt request bit Not used (returns "0" when read) (Do not write "1" to this bit) 0: No interrupt request issued 1: Interrupt request issued Fig 20. Structure of Interrupt-related registers Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 22 of 70 7549 Group Key Input Interrupt (Key-On Wakeup) A key-on wakeup interrupt request is generated by applying "L" level to any pin of port P1 that has been set to input mode. In other words, it is generated when the AND of input level goes from "1" to "0". An example of using a key input interrupt is shown in Figure 18, where an interrupt request is generated by pressing one of the keys provided as an active-low key matrix which uses ports P10 to P13 as input ports. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Port PXx "L" level output Port P1 pull-up control register Port P17 bit 7 = "0" Direction register = "1" ** Port P17 latch Falling edge detection * P17 output Key input interrupt request P16 output Port P17 key-on wakeup selection bit Port P1 pull-up control register Port P16 bit 6 = "0" Direction register = "1" * ** Port P16 latch Port P16 key-on wakeup selection bit Falling edge detection * P15 output Port P1 pull-up control register Port P15 bit 5 = "0" Direction register = "1" ** Port P15 latch Falling edge detection P14 output Port P15 key-on wakeup selection bit Port P1 pull-up control register Port P14 bit 4 = "0" Direction register = "1" * ** Port P14 latch Port P14 key-on wakeup selection bit Falling edge detection * P13 input Port P1 pull-up control register Port P13 bit 3 = "1" Direction register = "0" ** Port P13 latch Falling edge detection Port P1 Input read circuit P12 input Port P13 key-on wakeup selection bit Port P1 pull-up control register Port P12 bit 2 = "1" Direction register = "0" * ** Port P12 latch Port P12 key-on wakeup selection bit Port P1 pull-up control register Port P11 bit 1 = "1" Direction register = "0" * ** Port P11 latch Port P11 key-on wakeup selection bit Port P1 pull-up control register Port P10 bit 0 = "1" Direction register = "0" * ** Port P10 latch Port P10 key-on wakeup selection bit Falling edge detection Falling edge detection Falling edge detection P11 input P10 input * P-channel transistor for pull-up ** CMOS output buffer Fig 21. Connection example when using key input interrupt and port P1 block diagram Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 23 of 70 7549 Group Timers The 7549 Group has two 8-bit timers (timer 1 and timer 2) and one 16-bit timer (timer A). Timer 1 and timer 2 share the same 8-bit prescaler (prescaler 12). Each timer and prescaler has a separate timer latch and prescaler latch. The division ratio of every timer and prescaler is 1/(n+1), where n is the value of the timer latch or prescaler latch. The timers decrement at each count clock input. When the count value reaches "0", an underflow occurs at the next count pulse. The value of the corresponding timer latch is reloaded into the timer at underflow and counting is continued. When a timer underflow occurs, the interrupt request bit corresponding to each timer is set to "1". * Prescaler 12 (PRE12) Prescaler 12 is an 8-bit prescaler that counts the signal selected by the prescaler 12 count source selection bit. The count source can be selected from SOURCE/16 and XCIN input clock. Writing to prescaler 12 writes the value to both the prescaler latch and prescaler. Reading from prescaler 12 reads the prescaler 12 count value. The initial value is set to "FF16" after reset. The division ratio of prescaler 12 is 1/(n+1), where n is the setting value. Prescaler 12 cannot stop counting by software. * Timer 1 (T1) Timer 1 is an 8-bit timer that counts the prescaler 12 output. When Timer 1 underflows, the timer 1 interrupt request bit is set to "1". Writing to timer 1 writes the value to both the timer 1 latch and timer 1. Reading from timer 1 reads the timer 1 count value. The initial value is set to "0116" after reset. The division ratio of timer 1 is 1/(m+1), where m is the setting value. This gives that the division ratio of prescaler 12 and timer 1 is 1/((n+1) x (m+1)), where n is the prescaler 12 setting value and m is the timer 1 setting value. Timer 1 cannot stop counting by software. * Timer 2 (T2) Timer 2 is an 8-bit timer that counts the signal selected by the timer 2 count source selection bit. The count source can be selected from among SOURCE/16, /256, prescaler 12 output, and timer A output signal. Timer 2 counts the selected count source and sets the timer 2 interrupt request bit to "1" at underflow. When writing to timer 2, the value of the timer 2 write control bit can be used to select a write to both the timer 2 latch and timer 2 or a write to only the timer 2 latch. Reading from timer 2 reads the timer 2 count value. Timer 2 starts counting from "FF16" after reset. The division ratio of timer 2 is 1/(n+1), where n is the timer 2 setting value. Timer 2 stops when the timer 2 count stop bit is set to "1". When the P13/T2OUT output valid bit is set to "1", the polarity of the waveform output from the P13/T2OUT pin can be inverted at each timer 2 underflow. The output start level of the T2OUT pin can be selected using the T2OUT polarity switch bit. When this bit is set to 0, the output starts at "H" level. When this bit is set to "1", the output starts at "L" level. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY * Notes on Timers 1 and 2 (1) Reading from and Writing to Timer 1 and 2 and Prescaler 12 If the timer/prescaler count source clock and SOURCE are different clocks, the timers and prescaler cannot be read or written. Select the same clock to enable read and write operations. Note that timer 2 can be read and written even using a different clock while its counting is stopped. 1 Prescaler 12 and timer 1 cannot be read/written in the following conditions: Prescaler 12 count source: XCIN input clock SOURCE: Clock other than XCIN input clock 2 Timer 2 cannot be read/written during counting in the following conditions: Timer 2 count source: Prescaler 12 Prescaler 12 count source: XCIN input clock SOURCE: Clock other than XCIN input clock or Timer 2 count source: Timer A underflow Timer A count source: XCIN input clock SOURCE: Clock other than XCIN input clock or Timer 2 count source: Timer A underflow Timer A count source: low-speed on-chip oscillator output SOURCE: Clock other than low-speed on-chip oscillator (2) Count Source of Prescaler 12 The XCIN input clock can be selected as the prescaler count source only if the 32 kHz quartz crystal oscillator is selected by the oscillation method selection bit in FSROM1. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 24 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Timer mode register (TM: address 002B16, initial value: 0016) Not used (return "0" when read) Timer 2 count stop bit 0: Count start 1: Count stop P13/T2OUT output valid bit 0: Pulse output invalid (I/O port) 1: Pulse output valid T2OUT polarity selection bit 0: Start from "H" level 1: Start from "L" level Timer 2 write control bit 0: Write to latch and timer simultaneously 1: Write to only latch Timer A write control bit 0: Write to latch and timer simultaneously 1: Write to only latch Timer A count stop bit 0: Count start 1: Count stop Not used (return "0" when read) b7 b0 Timer count source set register (TCSS: address 002C16, initial value: 0016) Timer 2 count source selection bit b1 b0 0 0 : SOURCE/16 0 1 : SOURCE/256 1 0 : Prescaler 12 output 1 1 : Timer A underflow signal Timer A count source selection bit (Note 1) b4 b3 b2 0 0 0 : SOURCE/16 0 0 1 : SOURCE/2 0 1 0 : SOURCE/32 0 1 1 : SOURCE/64 1 0 0 : SOURCE/128 1 0 1 : SOURCE/256 1 1 0 : Low-speed on-chip oscillator output 1 1 1 : XCIN input clock (32kHz quartz crystal oscillation) Prescaler 12 count source selection bit 0 : SOURCE/16 1 : XCIN input clock (32kHz quartz crystal oscillation) Not used (return "0" when read) Note 1: SOURCE is the clock selected by bits 5 and 4 in the clock mode register (003716). The timer count sources are not affected by bits 7 and 6, the CPU clock dividing ratio select bits. Fig 22. Structure of timer mode register Fig 23. Structure of timer count source set register Data bus Prescaler 12 count source selection bit SOURCE/16 Prescaler 12 latch (8) Timer 1 latch (8) XCIN input clock (32kHz quartz crystal oscillation) Prescaler 12 (8) Timer 1 (8) Timer 1 interrupt request Data bus Timer 2 count source selection bit SOURCE/16 SOURCE/256 Timer 2 latch (8) Timer 2 write control bit Timer 2 (8) Timer 2 interrupt request Timer A underflow Timer 2 count stop bit "1" Q P13/T2OUT Toggle flip-flop T2OUT polarity selection bit Port P13 latch Port P13 direction register P13/T2OUT output valid bit Q "0" R T P13/T2OUT output valid bit Fig 24. Block diagram of timer 1 and timer 2 Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 25 of 70 7549 Group Timer A (TA) Timer A is a 16-bit timer and counts the signal selected by the timer A count source selection bit. The count source of Timer A can be selected from among SOURCE/2, /16, /32, /64, /128, /256, low-speed on-ship oscillator clock, and XCIN input clock. Timer A counts the selected count source and sets the timer A interrupt request bit to "1". When writing to timer A, the setting value of the timer A write control bit can be used to select a write to both the timer A latch and timer or a write to only the timer A latch. Reading from timer A reads the timer A count value. Be sure to write to and read from the low-order and the higher order of timer A in the following order: * Read Read the high-order of Timer A (TAH) first, and the loworder of Timer A (TAL) next. Always read both of the registers. * Write Write to the low-order of Timer A (TAL) first and the high-order of Timer A next. Always read both of the registers. Counting starts from "FFFF16" after reset. The division ratio of timer A is 1/(n+1), where n is the timer A setting value. Timer A stops when the timer A count stop bit is set to "1". Timer A can be used as the timing timer for input capture and output compare functions. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY * Notes on Timer A (1) Timer Value Setting When the timer A write control bit is set to "write to only latch", written data is written to only to the latch even when the timer is stopped. To set the initial setting value when the timer is stopped, select "Write to timer and latch simultaneously" beforehand. (2) Reading from and Writing to Timer A If the timer A count source clock and SOURCE are different clocks, timer A cannot be read or written during its counting. Select the same clock or set timer A to stop counting to enable read and write operations. * Timer A cannot be read/written in the following conditions: Timer A count source: XCIN input clock SOURCE: Clock other than XCIN input clock or Timer A count source: Low-speed on-chip oscillator output SOURCE: Clock other than low-speed on-chip oscillator (3) Count Source of Timer A The XCIN input clock can be selected as the count source of timer A only if the 32 kHz quartz crystal oscillator is selected by the oscillation method selection bit in FSROM1. Data bus SOURCE/2 SOURCE/16 SOURCE/32 SOURCE/64 SOURCE/128 SOURCE/256 Low-speed on-chip oscillator output Timer A (low-order) (8) Timer A (high-order) (8) Timer A (low-order) latch (8) Timer A (high-order) latch (8) Timer A write control bit Timer A interrupt request XCIN input clock (32 kHz quart crystal oscillator) Timer A count source selection bits Timer A count stop bit Compare Capture Fig 25. Block diagram of timer A Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 26 of 70 7549 Group Output compare 7549 group has 3-output compare channels. Each channel (0 to 2) has the same function and can be used to output waveform by using count value of Timer A. Three output compare channels share the registers with the input capture (one channel), but their individual circuits operate independently so that all the channels can be used at the same time. To use each compare channel, set "1" to the compare x (x = 0, 1, 2, 3) output port bit and set the port direction register corresponding to compare channel to output mode. The compare value for each channel is set to the capture/compare register (low-order) and capture/compare register (high-order). Writing to the register for each channel is controlled by setting value of capture/compare register RW pointer. Writing to each register is in the following order; 1. Set the corresponding compare latch to the capture/compare register RW pointer. 2. Write a value to the capture/compare register (low-order) and capture/compare register (high-order). (It doesn't care even if either low-order or high-order is written early.) 3. Set "1" to the compare latch y (y = 00, 01, 10, 11, 20, 21) re-load bit. When "1" is set to the compare latch y re-load bit, the value set to the compare register is loaded to compare latch when the next timer underflow. After loading, re-load bit is set to "0" automatically. When the count value of timer A matches the compare latch setting value, a trigger to the compare output circuit is generated. The trigger can be enabled or disabled using the compare x trigger enable bit. When the compare x trigger enable bit is set to 1, the output waveform from the port is as follows. * When the value of the compare x output level latch is "0" High level at compare latch x0 match Low level at compare latch x1 match * When the value of the compare x output level latch is "1" Low level at compare latch x0 match High level at compare latch x1 match The output waveform does not change if the compare x trigger enable bit is set to 0, so the port output remains fixed at high or low level. The compare output level of each channel can be confirmed by reading the compare x output status bit. Compare interrupt is available when match of each compare channel and timer count value. The interrupt request from each channel can be disabled or enabled by setting value of compare latch y interrupt source selection bit. * Notes on Output Compare (1) If timer A is stopped, when a value is written to the capture/ compare register it is immediately transferred to the compare latch. In addition, if timer A is stopped and the compare x trigger enable bit is set to "1", the output latch is initialized. (2) Do not write the same data to both of compare latch x0 and x1. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (3) When setting value of the compare latch is larger than timer setting value, compare match signal is not generated. Accordingly, the output waveform is fixed to "L" or "H" level. However, when setting value of another compare latch is smaller than timer setting value, this compare match signal is generated. Accordingly, compare interrupt occurs. (4) When the compare x trigger enable bit is cleared to "0" (disabled), the match trigger to the waveform output circuit is disabled, and the output waveform can be fixed to "L" or "H" level. However, in this case, the compare match signal is generated. Accordingly, compare interrupt occurs. b7 b0 Capture/Compare register (low-order) (CRAL: address 001016, initial value: 0016) Capture/Compare register (high-order) (CRAH: address 001116, initial value: 0016) b7 b0 Fig 26. Structure of capture/compare register b7 b0 Capture/Compare register RW pointer (CCRP: address 001216, initial value: 0016) Capture/Compare register RW pointer b2 b1 b0 0 0 0 : Compare latch 00 0 0 1 : Compare latch 01 0 1 0 : Compare latch 10 0 1 1 : Compare latch 11 1 0 0 : Compare latch 20 1 0 1 : Compare latch 21 1 1 0 : Capture latch 00 1 1 1 : Capture latch 01 Not used (returns "0" when read) Fig 27. Structure of capture/compare register RW pointer b7 b0 Compare register re-load register (CMPR: address 002D16, initial value: 0016) Compare latch 00, 01 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 10, 11 re-load bit 0: Re-load disabled 1: Re-load at next underflow Compare latch 20, 21 re-load bit 0: Re-load disabled 1: Re-load at next underflow Not used (returns "0" when read) Fig 28. Structure of compare register re-load register b7 b0 Capture/Compare port register (CCPR: address 002E16, initial value: 0016) Capture input port bits 0: Capture from P03 1: Low-speed on-chip oscillator/16 Compare 0 output port bit 0: P10 is I/O port 1: P10 is Compare 0 output Compare 1 output port bit 0: P11 is I/O port 1: P11 is Compare 1 output Compare 2 output port bit 0: P12 is I/O port 1: P12 is Compare 2 output Not used (returns "0" when read) Fig 29. Structure of capture/compare port register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 27 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Compare output mode register (CMOM: address 001316, initial value: 0016) Compare 0 output level latch 0: Positive 1: Negative Compare 1 output level latch 0: Positive 1: Negative Compare 2 output level latch 0: Positive 1: Negative Compare 0 trigger enable bit 0: Disabled 1: Enabled Compare 1 trigger enable bit 0: Disabled 1: Enabled Compare 2 trigger enable bit 0: Disabled 1: Enabled Not used (returns "0" when read) Fig 30. Structure of compare output mode register b7 b0 Capture/Compare status register (CCSR: address 002F16, initial value: 0016) Compare 0 output status bit 0: "L" level output 1: "H" level output Compare 1 output status bit 0: "L" level output 1: "H" level output Compare 2 output status bit 0: "L" level output 1: "H" level output Capture 0 status bit 0: latch 00 captured 1: latch 01 captured Not used (returns "0" when read) Fig 31. Structure of capture/compare status register b7 b0 Compare interrupt source register (CISR: address 003016, initial value: 0016) Compare latch 00 interrupt source bit Compare latch 01 interrupt source bit Compare latch 10 interrupt source bit Compare latch 11 interrupt source bit Compare latch 20 interrupt source bit Compare latch 21 interrupt source bit Not used (returns "0" when read) 0: Disabled 1: Enabled Fig 32. Structure of compare interrupt source register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 28 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Compare latch 00 Compare latch 01 P10/CMP0 Timer A latch Output waveform latch 0 Timer A counter Compare channel 0 P11/CMP1 Compare channel 1 Compare channel 2 P12/CMP2 Fig 33. Block diagram of compare output circuit Data bus Capture/Compare register R/W pointer (001216, bits 0 to 2) Compare buffer 00 (16) Compare latch 00, 01 reload bit (002D16, bit 0) Compare 0 output port selection bit (001E16, bit 2) I/O port P10/CMP0 Compare buffer 01 (16) Compare latch 00 (16) Compare 0 output status bit (002F16, bit 0) Output waveform latch 0 Compare 0 output level latch (001316, bit 0) Compare interrup Compare latch 00 interrupt source selection bit (003016, bit 0) Compare latch 01 interrupt source selection bit (003016, bit 1) Compare 0 trigger enable bit (001316, bit 3) Compare latch 01 (16) Compare register Timer A counter (16) Fig 34. Block diagram of compare channel 0 Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 29 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Timer A count clock Timer A underflow Timer A count value 000C Compare latch 00 Compare latch 01 Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 0 Re-load the count value 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B 000B 0005 Note: Compare interrupt occurs only for the interrupt source selected by Compare interrupt source register. Fig 35. Output compare mode (general waveform) Timer A count clock Timer A underflow Timer A count value 000C Compare latch 00 Compare latch 01 Compare latch 00 write Compare latch 01 write Compare latch 00, 01 re-load bit Compare latch 00, 01 re-load signal Compare 00 match Compare 01 match Compare output Compare interrupt Compare status bit 0 1 0 Re-load the count value 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B 000B 0005 000E 000C 1 0 Fig 36. Output compare mode (compare register write timing) Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 30 of 70 7549 Group Input capture 7549 group has 1-input capture channel and can be used to capture count value of Timer A. Input capture shares the registers with three output capture channels, but their individual circuits operate independently so that all the channels can be used at the same time. To use input capture, set the input capture port selection bits. If P03 is selected, set the P03 direction register to 0. When an input capture trigger is input to the input capture circuit, the count value of timer A is saved to the capture latches. The timer count value at the rising edge of the external input trigger is saved to capture latch 00, and the timer count value at the falling edge of the external input trigger is saved to capture latch 01. Capture latch 00 and capture latch 01 can be read using the following procedure. 1. Set the capture/compare register R/W pointer to the read target address. 2. Read the high-order bits of the capture/compare registers, then read the low-order bits of the capture/compare registers. (Read both the capture/compare registers in the sequence of high-order bits followed by low-order bits.) The count value of timer can be retained by software by capture y (y = 00, 01, 10, 11) software trigger bit too. When "1" is set to this bit, count value of timer is retained to the corresponded capture latch. When reading from the capture y software trigger bit is executed, "0" is read out. * Notes on Input Capture * When the low-speed on-chip oscillator output or XCIN input clock is selected as the count source of timer A, input capture can be used only if the same clock source is selected as SOURCE and as the count source of timer A. * When writing "1" to capture y software trigger bit of capture latch 00 and 01 at the same time, or external trigger and software trigger occur simultaneously, if capture latches 00 and 01 are input simultaneously, the set value of capture 0 status bit is undefined. * When setting the interrupt active edge selection bit and noise filter clock selection bit of captupe 0 the interrupt request bit may be set to "1". When not requiring the interrupt occurrence synchronized with these setting, take the following sequence. (1) Set the capture interrupt enable bit to "0" (disabled). (2) Set the interrupt edge selection bit or noise filter clock selection bit. (3) Set the corresponding interrupt request bit to "0" after 1 or more instructions have been executed. (4) Set the capture interrupt enable bit to "1" (enabled). * When the capture interrupt is used as the interrupt for return from stop mode, set the capture 0 noise filter clock selection bits to "00 (Filter stop)". Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Capture software trigger register (CSTR: address 003116, initial value: 0016) Capture latch 00 software trigger bit Capture 00 software trigger occurs by setting "1" to this bit. (returns "0" when read) Capture latch 01 software trigger bit Capture 01 software trigger occurs by setting "1" to this bit. (returns "0" when read) Not used (returns "0" when read) Fig 37. Structure of capture software trigger register b7 b0 Capture mode register (CAPM: address 003216, initial value: 0016) Capture 0 interrupt edge selection bits b1 b0 0 0 : Rising and falling edge 0 1 : Rising edge 1 0 : Falling edge 1 1 : Not available Capture 0 noise filter clock selection bits b1 b0 0 0 : Filter stop 0 1 : f (XIN) 1 0 : f (XIN)/8 1 1 : f (XIN)/32 Not used (returns "0" when read) Fig 38. Structure of capture mode register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 31 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Data bus Capture/Compare register RW pointer (001216, bits 0-2) Capture register Capture latch 00 (16) Capture latch 01 (16) Capture 0 status bit (002F16, bit 3) Capture latch 0x software trigger bits (003116, bits 0, 1) Digital filter Capture trigger Capture pointer Rising Falling Capture 0 interrupt edge selection bits (003216, bits 0, 1) Capture Interrupt Low-speed on-chip oscillator/16 P03/ CAP0 Capture 0 input port selection bit (002E16, bit 0) Capture latch 0 (16) Capture 0 noise filter clock selection bits (003216, bits 2, 3) Timer A counter (16) Fig 39. Block diagram of capture channel 0 Re-load the timer A count value Timer A underflow Capture input wave Timer A count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 Capture latch 01 Capture 0 interrupt Capture 0 status bit 1 0 1 0 1 0 XXXX XXXX 000A 0005 0001 000F 000C Fig 40. Capture input waveform (capture interrupt edge selection bit = "rising edge") Re-load the timer A count value Timer A underflow Capture input wave Timer A count value 000C 000B 000A 0009 0008 0007 0006 0005 0004 0003 0002 0001 0000 000F 000E 000D 000C 000B Overwrite Capture latch 00 Capture latch 01 Capture 0 interrupt Capture 0 status bit 1 0 1 0 1 0 XXXX XXXX 000A 0005 0001 000F 000C Fig 41. Capture input waveform (capture interrupt edge selection bit = "rising and falling edge") Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 32 of 70 7549 Group Serial Interface * Serial I/O Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register (bit 6) to "1". For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Data bus Serial I/O control register Receive buffer full flag (RBF) Receive interrupt request (RI) Address 001A16 Address 001816 Receive buffer register 1 P04/RXD Receive shift register 1 Shift clock Clock control circuit P06/SCLK Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator 1/4 Falling-edge detector Shift clock P05/TXD Transmit shift register Transmit buffer register Address 001816 Data bus 1/4 Address 001C16 SOURCE BRG count source selection bit P07/SRDY F/F Clock control circuit Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 001916 Fig 42. Block diagram of clock synchronous serial I/O Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 Receive enable signal SRDY Write pulse to receive/transmit buffer register 1 (address 001816) TBE = 0 TBE = 1 TSC = 0 RBF = 1 TSC = 1 Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes "1" . Fig 43. Operation of clock synchronous serial I/O function Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 33 of 70 7549 Group (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to "0". Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Data bus Serial I/O 1 control register Address 001A16 Receive buffer full flag (RBF) Receive interrupt request (RI) 1/16 PE FE SP detector Clock control circuit Serial I/O1 synchronous clock selection bit P06/SCLK Frequency division ratio 1/(n+1) Baud rate generator 1/4 Address 001C16 ST/SP/PA generator 1/16 P05/TXD Character length selection bit Transmit buffer register Address 001816 Data bus Transmit shift register Transmit shift completion flag (TSC) Transmit interrupt source selection bit Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 UART control register Address 001B16 OE P04/RXD ST detector 7 bits 8 bits Address 001816 Receive buffer register Character length selection bit Receive shift register SOURCE BRG count source selection bit Fig 44. Block diagram of UART serial I/O Transmit or receive clock Transmit buffer write signal TBE=0 TSC=0 TBE=1 Serial output TXD ST D0 D1 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) SP ST D0 D1 SP * Generated at 2nd bit in 2-stop-bit mode TBE=0 TBE=1 TSC=1* Receive buffer read signal RBF=1 Serial input RXD ST D0 D1 SP ST D0 RBF=0 RBF=1 D1 SP Notes 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes "1", can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Fig 45. Operation of UART serial I/O function Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 34 of 70 7549 Group [Transmit buffer register/receive buffer register (TB/ RB)] 001816 The transmit buffer register and the receive buffer register are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is "0". [Serial I/O status register (SIOSTS)] 001916 The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to "0" when the receive buffer register is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing "0" to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. Bits 0 to 6 of the serial I/O status register are initialized to "0" at reset, but if the transmit enable bit of the serial I/O control register has been set to "1", the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become "1". [Serial I/O control register (SIOCON)] 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. [UART control register (UARTCON)] 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P05/TxD pin. [Baud rate generator (BRG)] 001C16 The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY *Notes on Serial I/O * Serial I/O interrupt When setting the transmit enable bit to "1", the serial I/O transmit interrupt request bit is automatically set to "1". When not requiring the interrupt occurrence synchronized with the transmission enabled, take the following sequence. 1. Set the serial I/O transmit interrupt enable bit to "0" (disabled). 2. Set the transmit enable bit to "1". 3. Set the serial I/O transmit interrupt request bit to "0" after 1 or more instructions have been executed. 4. Set the serial I/O transmit interrupt enable bit to "1" (enabled). * I/O pin function when serial I/O is enabled. The functions of P06 and P07 are switched with the setting values of a serial I/O mode selection bit and a serial I/O synchronous clock selection bit as follows. (1) Serial I/O mode selection bit "1" : Clock synchronous type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit "0" : P06 pin turns into an output pin of a synchronous clock. "1" : P06 pin turns into an input pin of a synchronous clock. Setup of a SRDY output enable bit (SRDY) "0" : P07 pin can be used as a normal I/O pin. "1" : P07 pin turns into a SRDY output pin. (2) Serial I/O mode selection bit "0" : Clock asynchronous (UART) type serial I/O is selected. Setup of a serial I/O synchronous clock selection bit "0" : P06 pin can be used as a normal I/O pin. "1" : P06 pin turns into an input pin of an external clock. When clock asynchronous (UART) type serial I/O is selected, it is P07 pin. It can be used as a normal I/O pin. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 35 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Serial I/O status register (SIOSTS: address 001916, initial value: 8016) Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift inprogress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) b7 b0 Serial I/O control register (SIOCON: address 001A16, initial value: 0016) BRG count source selection bit (CSS) 0: SOURCE 1: SOURCE/4 Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. SRDY output enable bit (SRDY) 0: P07 pin operates as ordinary I/O pin 1: P07 pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P04 to P07 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P04 to P07 operate as serial I/O pins) b7 b0 UART control register (UARTCON: address 001B16, initial value: E016) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits P05/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig 46. Structure of serial I/O1-related registers Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 36 of 70 7549 Group A/D Converter The functional blocks of the A/D converter are described below. [AD conversion register] AD The A/D conversion register is a read-only register that stores the result of A/D conversion. Do not read out this register during an A/D conversion. [AD control register] ADCON The AD control register controls the A/D converter. Bit 2 to 0 are analog input pin selection bits. Bit 3 is the AD conversion clock selection bit. When "0" is set to this bit, the A/D conversion clock is SOURCE/2 and the A/D conversion time is 122 cycles of SOURCE. When "1" is set to this bit, the A/D conversion clock is SOURCE and the A/D conversion time is 61 cycles of SOURCE. Bit 4 is the AD conversion completion bit. The value of this bit remains at "0" during A/D conversion, and changes to "1" at completion of A/D conversion. A/D conversion is started by setting this bit to "0". [Comparison voltage generator] The comparison voltage generator divides the voltage between VSS and VCC by 1024, and outputs the divided voltages. [Channel selector] The channel selector selects one of ports P17/AN7 to P10/AN0, and inputs the voltage to the comparator. [Comparator and control circuit] The comparator and control circuit compares an analog input voltage with the comparison voltage and stores its result into the AD conversion register. When A/D conversion is completed, the control circuit sets the AD conversion completion bit and the A/ D interrupt request bit to "1". Because the comparator is constructed linked to a capacitor, set SOURCE in order that the A/D conversion clock is 250 kHz or over during A/D conversion. * Notes on A/D converter As for AD translation accuracy, on the following operating conditions, accuracy may become low. (1) When VCC voltage is lower than [ 3.0 V ], the accuracy at the low temperature may become extremely low compared with that at room temperature. When the system would be used at low temperature, the use at VCC = 3.0 V or more is recommended. (2) When XCIN or the low-speed on-chip oscillator is selected as SOURCE, the A/D converter cannot be used. b7 b0 Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY AD control register (ADCON: address 003416, initial value: 1016) Analog input pin selection bits 000: P10/AN0 001: P11/AN1 010: P12/AN2 011: P13/AN3 100: P14/AN4 101: P15/AN5 110: P16/AN6 111: P17/AN7 AD conversion clock selection bit 0: SOURCE/2 1: SOURCE AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (returns "0" when read) Fig 47. Structure of AD control register Read 8-bit (Read only address 003516) b7 b0 (Address 003516) b9 b8 b7 b6 b5 b4 b3 b2 Read 10-bit (read in order address 003616, 003516) b7 (Address 003616) (Address 003516) b0 b9 b8 b7 b0 b7 b6 b5 b4 b3 b2 b1 b0 Note: High-order 6-bit of address 003616 returns "0" when read. Fig 48. Structure of AD conversion register Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 37 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Data bus AD control register (Address 003416) b7 b0 3 A/D control circuit P10/AN0 P11/AN1 P12/AN2 P13/AN3 P14/AN4 P15/AN5 P16/AN6 P17/AN7 Channel selector A/D interrupt request Comparator AD conversion register (high-order) AD conversion register (low-order) 10 Resistor ladder (Address 003616) (Address 003516) SOURCE SOURCE/2 VCC VSS Fig 49. Block diagram of A/D converter Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 38 of 70 7549 Group Watchdog Timer The watchdog timer gives a means for returning to a reset status when the program fails to run on its normal loop due to a runaway. The watchdog timer consists of an 8-bit watchdog timer H and an 8-bit watchdog timer L, being a 16-bit counter. The operation of the watchdog timer is controlled by bits 2 to "0" in function set ROM data 2 and the watchdog timer control register. * Watchdog timer disable bit When the watchdog timer disable bit (bit 1 in function set ROM data 2(FSROM2)) is set to "0", the watchdog timer is enabled and starts counting after reset. Setting this bit to "1" does not operate the watchdog timer. This bit cannot be rewritten by executing the instruction. To use the watchdog timer, always set this bit to "0". After reset, the watchdog timer cannot start counting by a program. * Watchdog timer source clock selection bit The count source of the watchdog timer is selected by the watchdog timer source clock selection bit (bit 0 in FSROM2). This bit cannot be rewritten by executing the instruction. When this bit is set to "0", the count source is always set to the low-speed on-chip oscillator output/16. When this bit is set to "1", the count source is set to SOURCE/ 16. SOURCE is changed by setting the clock selection bits (bits 5 and 4 in the clock mode register (CLKM: address 003716)). * Watchdog timer H count source selection bit The count source of watchdog timer H is selected by the watchdog timer control register (WDTCON: address 003916). When the watchdog timer H count source selection bit (bit 7 in WDTCON) is set to "0", the count source is set to an underflow signal from watch dog timer L. When this bit is set to "1", the clock selected as the count source of watchdog timer L is input to watchdog timer H. The initial value of this bit after releasing reset can be set by the bit 2 in FSROM2. * Watchdog Timer Operation Resetting or writing any data to WDTCON sets watchdog timer H to "FF16" and watchdog timer L to "FF16". When the watchdog timer starts, the selected clock is counted and internal reset occurs by the watchdog timer H underflow. Writing to WDTCON is usually programmed to be performed before underflow. Reading WDTCON reads the values of the high-order 6 bits in the watchdog timer H counter and the watch dog timer count source selection bit. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY The following shows the time to watchdog timer underflow after writing to the watchdog timer control register. The example applies when the XIN input clock is selected as SOURCE and f(XIN) = 8 MHz. * Watchdog timer H count source selection bit = 0: 131.072 ms * Watchdog timer H count source selection bit = 1: 512 s b7 b0 Function set ROM data 2 FSROM2 (FFDA16) Watchdog timer source clock selection bit 0 : Low-speed on-chip oscillator/16 1 : System clock/16 Watchdog timer start selection bit 0 : Start watchdog timer 1 : Stop watchdog timer Watchdog timer H count source initial value selection bit 0 : Initial value of bit 7 of WDTCON after reset release is "0" 1 : Initial value of bit 7 of WDTCON after reset release is "1" STP instruction function selection bit 0 : System enters into the stop mode at the STP instruction execution 1 : Internal reset occurs at the STP instruction execution Low-speed on-chip oscillator control bit (Note 1) 0 : Stop of low-speed on-chip oscillator disabled 1 : Stop of low-speed on-chip oscillator enabled Set "0" to these bits certainly. Note 1: If "0" is set to this bit, it is not possible to write "1" to bit 0 in the clock mode register. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed. Fig 50. Structure of Function set ROM data 2 b7 b0 Watchdog timer control register (Note) (WDTCON: address 003916, initial value: X01111112) Watchdog timer H (read only for high-order 6-bit) Not used (returns "0" when read) Watchdog timer H count source selection bit 0 : Watchdog timer L underflow 1 : Low-speed on-chip oscillator/16 or SOURCE/16 Note: The initial value of this register is changes by setting of function set ROM data 2. Fig 51. Structure of watchdog timer control register Initial value setting after releasing reset Watchdog timer H count source initial value selection bit (bit 2 of FSROM2) Data bus "FF16" is set at WDTCON writing Watchdog timer H (8) Watchdog timer source clock selection bit (bit 0 of FSROM2) SOURCE 1/16 Low-speed on-chip oscillator Watchdog timer H count source selection bit (bit 7 of WDTCON) "FF16" is set at WDTCON writing Watchdog timer L (8) Watchdog timer start selection bit (bit 1 of FSROM2) STP instruction function selection bit (bit 3 of FSROM2) Reset circuit STP Instruction Reset pin input Internal reset FSROM2: Function set ROM data 2 WDTCON: Watchdog timer control register CPUM: CPU mode register Fig 52. Block diagram of watchdog timer Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 39 of 70 7549 Group * Notes on Watchdog Timer (1) The watchdog timer operates in wait mode. To prevent underflow, write to the watchdog timer control register. The watchdog timer stops in stop mode, but starts counting at the same time as exiting stop mode. After exiting stop mode, it continues counting during oscillation stabilization time. To prevent underflow during the period, the watchdog timer H count source selection bit (bit 7) in the watchdog timer control register (address 003916) should be set to "0" before executing the STP instruction. Note that the watchdog timer continues counting even if the STP instruction is executed in the following two conditions: 1 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in FSROM2) Source clock of the watchdog timer: Low-speed on-chip oscillator/16 (bit 0 in FSROM2) 2 Stopping the low-speed on-chip oscillator: Disabled (bit 4 in FSROM2) Source clock of the watchdog timer: SOURCE (bit 0 in FSROM2) SOURCE: Low-speed on-chip oscillator (bits 5 and 4 in CLKM) (2) STP instruction function selection bit The function of the STP instruction can be selected by the bit 2 in FSROM2. This bit cannot be used for rewriting by executing the STP instruction. * When this bit is set to "0", stop mode is entered by executing the STP instruction. * When this bit is set to "1", internal reset occurs by executing the STP instruction. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 40 of 70 7549 Group Power-on Reset Circuit Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. To use the built-in power-on reset circuit, leave the RESET pin open (the pull-up resistor is built-in). Low Voltage Detection Circuit The built-in low voltage detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the power source voltage drops below a set value (Typ.1.95 V). The low voltage detection circuit is valid by setting "1" to bit 0 of the function set ROM data 0. Also, when "1" is set to bit 2 of the function set ROM data 1, the low voltage detection circuit can be valid even in the stop mode. The low voltage detection circuit is stopped in the stop mode by setting "0" to this bit, so that the power dissipation is reduced. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY VCC (Note) Power-on reset circuit output Internal reset signal Reset state Power-on Reset released Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Fig 53. Operation waveform diagram of power-on reset circuit VCC Reset voltage (Typ:1.95V) Internal reset signal Microcomputer starts operation by the built-in on-chip oscillator. Fig 54. Operation waveform diagram of low voltage detection circuit Low-speed on-chip oscillator clock Internal CPU clock RESET Internal reset signal SYNC Address ? ? ? ? ? ? ? ? ? ? ? FFFC ADL FFFD ADH,ADL ADH Reset address from the vector table Data 9 to 16 cycles of internal CPU clock Fig 55. Timing diagram at reset Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 41 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) Port P0 direction register (P0D) Port P1 direction register (P1D) Port P2 direction register (P2D) Port P3 direction register (P3D) Port P0 drive capacity control register (DCCR) Port P0 pull-up control register (PULL0) Port P1 pull-up control register (PULL1) Key-on wakeup input selection register (KEYS) Capture/Compare register (low-order) (CRAL) Capture/Compare register (high-order) (CRAH) Capture/Compare register R/W pointer (CCRP) Compare output mode register (CMOM) Timer A (low-order) (TAL) Timer A (high-order) (TAH) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Prescaler 12 (PRE12) Timer 1 (T1) Timer 2 (T2) Timer mode register (TM) Timer count source set register (TCSS) Compare register re-load register (CMPR) Capture/Compare port register (CCPR) Capture/Compare status register (CCSR) Compare interrupt source set register (CISR) Capture software trigger register (CSTR) Capture mode register (CAPM) AD control register (ADCON) Clock mode register (CLKM) Oscillation stop detection register (CLKSTP) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2) 000116 000316 000516 000716 000C16 000D16 000E16 000F16 001016 001116 001216 001316 001416 001516 001916 001A16 001B16 002816 002916 002A16 002B16 002C16 002D16 002E16 002F16 003016 003116 003216 003416 003716 003816 003916 003A16 003B16 003C16 003D16 003E16 003F16 Note 4 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 1 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0016 FF16 FF16 0016 0016 0016 0016 0016 0016 0016 0016 0 0 0 0 0 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 0 0 1 0016 0016 0016 0016 0016 0016 0016 Notes 1: X : Undefined 2: The content of other registers is undefined when the microcomputer is reset. The initial values must be surely set before you use it. 3: Do not access to the SFR area including nothing. 4: When the setting by the function set ROM data 2 (FSROM2) is performed, the initial values of this bit at reset are changed. Fig 56. Timing diagram at reset Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 42 of 70 7549 Group Clock Circuit The clock circuit includes the XIN clock (ceramic oscillator or crystal oscillator can be used), XCIN clock (32 kHz oscillator can be used), external clock input, high-speed on-chip oscillator, and low-speed on-chip oscillator. Pins P20/XOUT/XCOUT and P21/XIN/XCIN can be shared for the ports, XIN oscillation, and XCIN oscillation. Use the oscillation method selection bits (bits 1 and bit 0 in function set ROM data 1 (FSROM1)) to set the function of these pins. * Ceramic Resonator or Crystal Oscillator Set the oscillation method selection bits (bits 1 and bit 0 in FSROM1) to "012", and connect the resonator (or the oscillator) and external circuit with the shortest wiring length possible. The constants of the oscillator circuit differ depending on the resonator. Use the values recommended by the resonator manufacturer. (An external feedback resistor may be necessary under some conditions.) Setting the XIN/XCIN oscillation control bit to "0" starts oscillation. This bit is sets to "0" after reset. * 32 kHz Crystal Oscillator Set the oscillation method selection bits to "102", and connect the 32 kHz crystal oscillator and external circuit with the shortest wiring length possible. The constants of the oscillator circuit differ depending on the resonator. Use the values recommended by the resonator manufacturer. (An external feedback resistor may be necessary under some conditions.) Setting the XIN/XCIN oscillation control bit to "0" starts oscillation. This bit is sets to "0" after reset. * External Clock Input Set the oscillation method selection bits to "112", and connect the clock source to the P20/XOUT pin. In this case, the P21/XIN pin can be used as an I/O port. * High-Speed On-Chip Oscillator The high-speed on-chip oscillator is stopped after reset. Setting the high-speed on-chip oscillator oscillation control bit (bit 1 in CLKM) to "0" starts oscillation. This bit is sets to "1" after reset. * Low-Speed On-Chip Oscillator The low-speed on-chip oscillator automatically starts oscillating after reset. Setting the low-speed on-chip oscillator oscillation control bit (bit 0 in CLKM) to "1" stops oscillation. This bit is sets to "0" after reset. If the low-speed on-chip oscillator control bit (bit 4 in FSROM2) is set to "0" and stopping the low-speed on-chip oscillator is disabled, the low-speed on-chip oscillator oscillation control bit cannot be set to "1" and oscillation cannot be stopped. Also, the oscillator does not stop even when the STP instruction is executed. * Using No Oscillator Pins (P20 as output port and P21 as I/O port) To use only an internal on-chip oscillator, set the oscillation method selection bits to "002". The P20/XOUT pin can be used as an output port and the P21/XIN pin can be used as an I/O port. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Function set ROM data 1 FSROM1 (FFD916) Oscillation method selection bits (Note 1) b1 b0 0 0: Clock pins not used (P20/XOUT and P21/XIN are used as I/O ports) 0 1: Ceramic resonator or quarts-crystal oscillator 1 0: 32 kHz quarts-crystal oscillator 1 1: External clock input (P21/XIN pin is used as I/O port) Low voltage detection circuit valid bit in the stop mode (Note 2) 0: Low voltage detection circuit invalid in the stop mode 1: Low voltage detection circuit valid in the stop mode Set "0" to these bits certainly. Set "1" to this bit certainly. Notes 1: The P20/XOUT and P21/XIN pins build in an on-chip oscillator. Even if these pins are used as I/O ports, the oscillator circuit is enabled when the MCU's Vcc voltage drops below the operation limit voltage. In this case these pins may output undefined values. 2: When the Low voltage detection circuit is set to be valid in the stop mode, the dissipation current in the stop mode is increased. Fig 57. Structure of function set ROM data 1 M37549 XIN XOUT Rd CIN COUT Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists onchip, insert a feedback resistor between XIN and XOUT following the instruction. Fig 58. External circuit of ceramic resonator M37549 XCIN XCOUT Rd CIN COUT Insert a damping resistor if required. The resistance will vary depending on the oscillator and the oscillation drive capacity setting. Use the value recommended by the maker of the oscillator. Also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip though a feedback resistor exists on-chip, insert a feedback resistor between XIN and XOUT following the instruction. Fig 59. External circuit of 32 kHz quarts-crystal oscillator M37549 P21 XOUT Connect the external clock to the P20/XOUT pin, not the P21/XIN pin. I/O port External oscillation circuit Vcc Vss Fig 60. External clock input circuit Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 43 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY b7 b0 Clock mode register (CLKM: address 003716, initial value: 0216) Low-speed on-chip oscillator oscillation control bit (Notes 1, 2, and 4) 0: Oscillation start 1: Oscillation stop High-speed on-chip oscillator oscillation control bit (Notes 2 and 4) 0: Oscillation start 1: Oscillation stop XIN oscillation control bit (Notes 2 and 4) 0: Oscillation start 1: Oscillation stop Oscillation stabilization time set bit after release of the STP instruction 0: Timer 1 set to "0116" and prescaler 12 to "FF16" automatically 1: Un-automatically Clock selection bits (Notes 3 and 4) b5 b4 0 0 : Low-speed on-chip oscillator 0 1 : High-speed on-chip oscillator 1 0 : XIN/XCIN oscillation, External clock 1 1 : Not available Clock division ratio selection bit b7 b6 0 0 : SOURCE/8 (low-speed mode) 0 1 : SOURCE/4 (middle-speed mode) 1 0 : SOURCE/2 (high-speed mode) 1 1 : No division (double-speed mode) Notes 1: When stopping the low-speed on-chip oscillator is disabled by setting the low-speed on-chip oscillator control bit (bit 4 in FSROM2), "1" cannot be written to this bit. The low-speed on-chip oscillator does not stop even in stop mode. 2: "1" cannot be written to the oscillation control bits (bits 2 to 0) of the clock selected as SOURCE by the clock selection bits. 3: When "oscillation pins not used" is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), "102" cannot be written to these bits. 4: Do not change the values of the clock selection bits and the clock oscillation control bits at the same time using a single instruction. Always use different instructions to rewrite these values. Fig 61. Structure of clock mode register * Note on Clock Circuit * Switching to XIN/XCIN Oscillator After a reset is cleared, operation starts using the low-speed onchip oscillator. When switching to XIN/XCIN oscillator, make sure to set a sufficient wait duration with the on-chip oscillator to allow the XIN/XCIN oscillator to stabilize. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 44 of 70 7549 Group Oscillation Control * Clock mode register Clock mode register contains the oscillation control bits of each oscillation circuits, clock selection bits and etc * Clock selection bits SOURCE can be selected by the clock selection bits (bits 5 and 4 in clock mode register). SOURCE can be selected from lowspeed on-chip oscillator, high-speed on-chip oscillator, XIN/XCIN oscillaton or external clock input by the clock selection bits. SOURCE is also used to the clock for peripheral functions. When the oscillation method selection bits (bits 1 and 0 in FSROM1) is set to "002" (oscillation pins not used), setting the clock selection bits to "102" (XIN/XCIN oscillation, external clock input) is disabled. * Clock division ratio selection bit The internal clock is generated by dividing SOURCE. Select the division ratio using the clock division ration selection bits (bits 7 and 6 in CLKM). The division ratio can be selected from among SOURCE/8 (low-speed mode), /4 (middle-speed mode), /2 (high-speed mode), and no division (double-speed mode). Table 9 shows the division ratio (mode) settings. When releasing reset, the low-speed on-chip oscillator is selected as SOURCE, and SOURCE/8 is selected as the internal clock. The high-speed on-chip oscillator is stopped at this time. If an oscillation circuit is connected to the clock pin, oscillation starts. To switch SOURCE to XIN/XCIN oscillation, generate wait time using the on-chip oscillator until the oscillation is stabilized. Table 9 Setting the clock division (mode) CLKM Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY FSROM1 Clock selection bits Bit 5, 4 10 10 10 10 10 10 10 10 10 10 10 10 01 01 01 01 00 00 00 00 XIN/XCIN oscillation control bit Bit 2 0 0 0 0 0 0 0 0 - - - - - - - - - - - - High-speed on-chip Low-speed on-chip oscillator oscillation oscillator oscillation control bit control bit Bit 1 - - - - - - - - - - - - 0 0 0 0 - - - - Bit 0 - - - - - - - - - - - - - - - - 0 0 0 0 Oscillation method selection bits Bit 1, 0 01 01 01 01 10 10 10 10 11 11 11 11 - - - - - - - - FSROM2 Low-speed onchip oscillator control bit Bit 4 - - - - - - - - - - - - - - - - 1/0 1/0 1/0 1/0 bit Clock division SOURCE Mode XIN Double-speed High-speed Middle-speed Low-speed XCIN Double-speed High-speed Middle-speed Low-speed External clock Double-speed High-speed Middle-speed Low-speed High-speed Double-speed on-chip High-speed oscillator Middle-speed Low-speed Low-speed Double-speed on-chip High-speed oscillator Middle-speed Low-speed ratio selection bits Bit 7, 6 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 11 10 01 00 -: can be "0" or "1", no change in outcome Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 45 of 70 7549 Group * Stop mode When the STP instruction is executed, the internal clock stops at an "H" level and the XIN/XCIN and on-chip oscillator stops. At this time, timer 1 is set to "0116" and prescaler 12 is set to "FF16" when the oscillation stabilization time set bit after release of the STP instruction is "0". On the other hand, timer 1 and prescaler 12 are not set when the above bit is "1". Accordingly, set the wait time fit for the oscillation stabilization time of the oscillator to be used. When an external interrupt is accepted, oscillation is restarted but the internal clock remains at "H" until timer 1 underflows. As soon as timer 1 underflows, the internal clock is supplied. This is because when a ceramic resonator is used, some time is required until a start of oscillation. In case oscillation is restarted by reset, no wait time is generated. So apply an "L" level to the RESET pin while oscillation becomes stable, or set the wait time by on-chip oscillator operation after system is released from reset until the oscillation is stabled. * Wait mode If the WIT instruction is executed, the internal clock stops at an "H" level, but the oscillator does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to "1" before the STP or WIT instruction is executed. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY * Note on Oscillation Control For use with the oscillation stabilization set bit after release of the STP instruction set to "1", set values in timer 1 and prescaler 12 after fully appreciating the oscillation stabilization time of the oscillator to be used. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 46 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Bits 0 and 1 of FSROM1: setting of the oscillation method setection bits "00": Clock pins not used P21/XIN/XCIN P20/XOUT/XCOUT "01": Ceramic or quartzcrystal oscillation P21/XIN/XCIN P20/XOUT/XCOUT "10": 32 kHz quartzcrystal oscillation P21/XIN/XCIN P20/XOUT/XCOUT "11": External clock input P21/XIN/XCIN P20/XOUT/XCOUT Port P21 control circuit Port P20 control circuit (Note 2) Rf (Note 2) Rf Port P21 control circuit XIN/XCIN oscillation control bit Noise filter "11": Double-speed mode Clock selection bits "10" SOURCE 1/2 1/4 1/8 "10": High-speed mode "01": Middle-speed mode "00": Low-speed mode Timing (Internal clock) High-speed on-chip oscillator (HSOCO) High-speed on-chip oscillator oscillation control bit Low-speed on-chip oscillator (LSOCO) Low-speed on-chip oscillator oscillation control bit It is not possible to write "1" to the low-speed on-chip oscillator oscillation control bit if low-speed on-chip oscillator stop has been disabled by bit 4 in FSROM2. Also, the low-speed on-chip oscillator does not stop even if the STP instruction is executed. "01" "00" Clock division ratio selection bits Peripheral function clock generation circuit (1/1 to 1/256) 1/1 to 1/256 1/16 XIN oscillation cannot be selected as SOURCE if clock pins not used is selected. Peripheral function Oscillation stabilization time set timer after release of the STP instruction Timer 1 Prescaler 12 Reset STP instruction S R Q Q S R STP instruction WIT instruction S R Q Reset Interrupt disable flag I Interrupt request Notes 1: The oscillation circuit is built in the P20/XOUT/XCOUT pin and the P21/XIN/XCIN pin. When the Vcc of the microcomputer is lower than the operation lower bound voltage even if these pins are used as I/O ports, the oscillation circuit is connected and undefined values may be output from these pins. 2: Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending on conditions. Fig 62. Block diagram of internal clock generating circuit Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 47 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY State transition of clock mode register CLKM (address: 003716) setting value and clock (When XIN oscillation is used. The same applies when XCIN oscillation and external clock input are used.) High-speed on-chip oscillator (HSOCO): oscillation start b1=0 Stop (b2=1) Stop (b0=1) XIN Oscillation (b2=0) HS O (b5 CO ,4= 0,1 ) XIN "S" * HSOCO LSOCO "S" xx01x101 XIN "O" * HSOCO LSOCO "S" xx01x001 3) b5 , (N 4 ote LSOCO Oscillation (b0=0) b2 b2,0 (Note 1) (N b0 ote 1 (N ote b0 1) (b5 O OC ) HS =0,1 ,4 S OU se RCE lec tio XIN n b2,0 (Note 1) ) XIN "S" * HSOCO LSOCO "O" xx01x100 b5 E RC OU n S ectio l se (b5 , (N 4=1, ote 0) 3) b2 O OC ,0) LS ,4=0 (b5 HS OC O p Sto 1) = b1 ( HSOCO "O" LSOCO "S" xx10x001 b1 b5 (No ,4 te 3 ) n tio illa sc 0) O= * XIN (b1 XIN "O" * HSOCO LSOCO "O" xx01x000 b5 ,4 ,4 Os (N b0 ote 1 XIN "S" HSOCO "O" * LSOCO xx00x100 b2 cill a (b1 tion =0 ) HS OC O S (b1 top =1 ) ) * XIN HSOCO "S" LSOCO "S" xx10x011 0 b1, te 1) o (N * XIN HSOCO "O" b5,4 LSOCO "O" (Note 3) xx10x000 XIN "O" HSOCO "O" * LSOCO xx00x000 b1 b1 (N b0 ote 1 b2 ,1 XIN oscillation: oscillation start (Note 3) b2=0 p Sto =1) LS (b0 (N ,0 b1 ) 1 ote ) b2 ,1 XIN "S" HSOCO "S" * LSOCO xx00x110 b2 b1 * XIN HSOCO "S" LSOCO "O" xx10x010 b5,4 (Note 3) XIN "O" HSOCO "S" * LSOCO xx00x010 Os (Note 2) Reset released on ati cill Os =0) (b0 XIN (b5,4=1,0) CO (Note 3) O cill a (b2 tion =0 ) LSOCO Low-speed on-chip oscillator (LSOCO): oscillation start b0=0 S (b2 top =1 ) (b5,4=0,0) XIN [Remarks] XIN "O" HSOCO "S" * LSOCO xx00x010 SOURCE selection b5,4 (Note 3) XIN, HSOCO, LSOCO, and respective oscillation and stop status in each mode are shown. The symbol (*) indicates SOURCE (oscillation) selected by the clock selection bits. "O" indicates oscillation and "S" indicates stopping. The values such as "xx00x010" indicate the values (binary) of the clock mode register in the mode. The arrow (bx) indicates a bit in the clock mode register, showing a transition by changing the bit values. Entering the mode should be performed according to the arrows. Wait mode and stop mode can be entered from all modes, and the original mode is returned after exiting. Wait mode * Low-speed on-chip oscillator: Status before executing WIT instruction is kept * High-speed on-chip oscillator: Status before executing WIT instruction is kept * XIN oscillation: Status before executing the WIT instruction is kept Stop mode * Low-speed on-chip oscillator: Stopped (Note 1) * High-speed on-chip oscillator: Stopped * XIN oscillation: Stopped Notes 1: When stopping the low-speed on-chip oscillator is disabled by the low-speed on-chip oscillator control bit (bit 4 in FSROM2), "1" cannot be written to the bit 0 in CLKM. The low-speed on-chip oscillator does not stop even in stop mode. 2: After releasing reset, the low-speed on-chip oscillator is selected as SOURCE and divided by 8 is selected as the CPU clock. 3: When the oscillation pins not used is set by the oscillation method selection bits (bits 1 and 0 in FSROM1), "10" cannot be written to bits 5 and 5 in CLKM. To use XIN oscillation as SOURCE, switch after XIN oscillation is stabilized. Supply a stable clock when an external clock is used. 4: Do not change the values of the clock selection bits (bits 5 and 4) in CLKM and the individual clock oscillation control bits (bits 2 to 0) at the same time using a singe instruction. Always use different instructions to rewrite these values. 5: Wait until the oscillation used in the destination mode is stabilized before entering. Fig 63. SOURCE state transition Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 48 of 70 7549 Group * Oscillation stop detection circuit The oscillation stop detection circuit is used for reset occurrence when a ceramic resonator or RC oscillation circuit stops by disconnection. To use this circuit, set an on-chip oscillator to be in active. The oscillation stop detection circuit is in active to set "1" to the XIN oscillation stop detection function active bit. When the oscillation stop detection circuit is enabled, the operation status of the XIN oscillator circuit is monitored using the low-speed on-chip oscillator, and if oscillation stop is detected the oscillation stop detection status bit is set to 1. If additionally the oscillation stop detection reset enable bit is set to "1", an internal reset is triggered when the oscillator stops operating. The oscillation stop detection status bit is not initialized by an oscillation stop detection reset and retains its value of 1. Since the oscillation stop detection status bit is initialized to "0" by an external reset, it is possible to determine if a reset was due to oscillation stop detection by checking the oscillation stop detection status bit. The XIN oscillation and external clock input are set as the clocks to detect the oscillation stop. Refer to the electrical characteristics for the frequencies to detect the oscillation stop. * Notes on Oscillation Stop Detection Circuit (1) Do not execute the transition to "state 2'a" shown in Figure 65 because in this "state 2'a", MCU is stopped without reset even when XIN oscillation is stopped. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (2) XIN oscillation stop detection function active bit is not cleared by the oscillation stop detection reset. Accordingly, the oscillation stop detection circuit is in active when system is released from internal reset cause of oscillation stop detection. (3) Oscillation stop detection status bit is initialized by the following operation. * External reset, power-on reset, low voltage detection reset, watchdog timer reset, and reset by STP instruction function * Write "0" data to the XIN oscillation stop detection function active bit. (4) The oscillation stop detection circuit is not included in the emulator MCU "M37549RLSS". b7 b0 Oscillation stop detection register (CLKSTP: address 003816, initial value: 0016) XIN oscillation stop detection function active bit 0: Detection function inactive 1: Detection function active Oscillation stop detection reset enable bit 0: Oscillation stop detection reset disabled 1: Oscillation stop detection reset enabled Oscillation stop detection status bit 0: Oscillation stop not detected 1: Oscillation stop detected Not used ("0" at reading) Fig 64. Structure of oscillation stop detection register SOURCE: XIN CLKM54 = 102 SOURCE: Low-speed on-chip oscillator (Note 4) XIN oscillation State 3 Low-speed on-chip oscillator :: enabled enabled CLKM54 = 002 (Note 1) Oscillation stop detection circuit is in active. (Note 3) CLKSTP 0 = 12 (Note 1) CLKSTP0 = 02 (CLKSTP2 is set to "0".) Reset released State 2 XIN oscillation : enabled Low-speed on-chip oscillator : enabled Reset state 1 XIN : enabled High-speed on-chip oscillator : stop Low-speed on-chip oscillator : enabled CLKSTP1 = 02 CLKSTP1 = 12 (Note 2) (CLKSTP2 is set to "0".) XIN oscillation State 2' Low-speed on-chip oscillator :: enabled enabled State 3' Low-speed on-chip oscillator : enabled State 3'a Oscillation stop detection reset disabled CLKM54=102 When oscillation stop is detected; CLKSTP2 is set to "1". Internal RESET does not occur. XIN oscillation : enabled Prohibitive state MCU stops when oscillation stops occurs. (Note 2) CLKM54=002 (Note 1) External reset (RESET="L") Power-on reset Low voltage detection reset Watchdog timer reset Reset by STP instruction function State 2'a (Note 2) Oscillation stop detection reset disabled When oscillation stop is detected; CLKSTP2 is set to "1". Internal RESET does not occur. State 3'c Return from oscillation stop detection reset CLKSTP2 is set to "1". So, return from oscillation stop reset can be confirmed. Reset released Reset state 2 XIN : enabled High-speed on-chip oscillator : stop Low-speed on-chip oscillator : enabled CLKSTP1= 12 (Note 2) CLKSTP1= 02 CLKSTP1 = 12 CLKSTP1 = 02 State 2'b Oscillation stop detection reset enabled When oscillation stop is detected; CLKSTP2 is set to "1". Internal RESET occurs. CLKM54 = 102 State 3'b Oscillation stop detection reset enabled When oscillation stop is detected; CLKSTP2 is set to "1". Internal RESET occurs. Oscillation stop is detected (internal reset) CLKM54 = 002 (Note 1) Notes on switch of clock (1) Executing the state transition after stabilizing XIN oscillation. (2) MCU cannot be returned by on-chip oscillator and its operation is stopped since internal reset does not occur at oscillation stop detected in state 2'a. Accordingly, do not execute the transition to state 2'a. (3) STP instruction cannot be used when oscillation stop detection circuit is in active. (4) The same applies when the high-speed on-chip oscillator is set as SOURCE. Make sure that the low-speed on-chip oscillator should also oscillate. When a reset occurs, the high-speed on-chip oscillator stops. Fig 65. State transition of oscillation stop detection circuit Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 49 of 70 7549 Group QzROM Writing Mode In the QzROM writing mode, the user ROM area can be rewritten while the microcomputer is mounted on-board by using a serial programmer which is applicable for this microcomputer. Table 10 lists the pin description (QzROM writing mode) and Figure 66 shows the pin connections. Table 10 Pin description (QzROM writing mode) Pin VCC, VSS RESET P21 /XIN P20 /XOUT P00 - P05 P11 - P17 P30, P31 CNVSS P10 P06 P07 Name Power source Reset input Clock input Clock output I/O port I/O Input Input Input Output I/O Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Refer to Figure 67 and Figure 68 for examples of a connection with a serial programmer. Contact the manufacturer of your serial programmer for serial programmer. Refer to the user's manual of your serial programmer for details on how to use it. Function Apply 1.8 to 5.5 V to VCC, and 0 V to VSS. Reset input pin. Set the same termination as the single-chip mode. Input "H" or "L" level signal or leave the pin open. VPP input ESDA I/O ESCLK input ESPGMB input Input I/O Input Input QzROM programmable power source pin. Serial data I/O pin. Serial clock input pin. Read/program pulse input pin. P14/AN4/KEY4 P15/AN5/KEY5 RESET RESET P16/AN6/KEY6 P17/AN7/KEY7 P20/XOUT/XCOUT GND VSS P21/XIN/XCIN VCC VPP VCC CNVSS P00(LED0)/INT0 P01(LED1)/INT1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 P13/AN3/KEY3/T2OUT P12/AN2/KEY2/CMP2 P11/AN1/KEY1/CMP1 P10/AN0/KEY0/CMP0 P31 P30 P07(LED7)/SRDY P06(LED6)/SCLK P05(LED5)/TxD P04(LED4)/RxD P03(LED3)/CAP0 P02(LED2) : Set the same termination as the single-chip mode. : QzROM pin ESPGMB ESCLK ESDA Package type: PRSP0024GA-A (24P2Q-A) M37549G3/G2/G1FP Fig 66. Pin connection diagram (M37549G3/G2/G1FP) Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 50 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY 7549 Group Vcc Vcc CNVSS 4.7 k 4.7 k P10 (ESDA) P06 (ESCLK) P07 (ESPGMB) RESET circuit *1 14 12 10 8 6 4 2 13 11 9 7 5 3 1 RESET Vss P21/XIN P20/XOUT Set the same termination as the single-chip mode. * 1: Open-collector buffer Note : For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF Fig 67. When using E8 programmer, connection example Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 51 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY 7549 Group T_VDD T_VPP 4.7 k T_TXD 4.7 k T_RXD P10 (ESDA) Vcc CNVSS T_SCLK T_BUSY N.C. T_PGM/OE/MD RESET circuit T_RESET GND P06 (ESCLK) P07 (ESPGMB) RESET Vss P21/XIN P20/XOUT Set the same termination as the single-chip mode. Note: For the programming circuit, the wiring capacity of each signal pin must not exceed 47 pF. Fig 68. When using programmer of Suisei Electronics System Co., LTD, connection example Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 52 of 70 7549 Group NOTES ON PROGRAMMING (1) Processor Status Register The contents of the processor status register (PS) after reset are undefined except for the interrupt disable flag I which is "1". After reset, initialize flags which affect program execution. In particular, it is essential to initialize the T flag and the D flag because of their effect on calculations. (2) Interrupts The contents of the interrupt request bit do not change even if the BBC or BBS instruction is executed immediately after they are changed by program because this instruction is executed for the previous contents. For executing the instruction for the changed contents, execute one instruction before executing the BBC or BBS instruction. (3) Decimal Calculations * For calculations in decimal notation, set the decimal mode flag D to "1", then execute the ADC instruction or SBC instruction. In this case, execute SEC instruction, CLC instruction or CLD in-struction after executing one instruction before the ADC instruction or SBC instruction. * In the decimal mode, the values of the N (negative), V (overflow) and Z (zero) flags are invalid. (4) Ports The values of the port direction registers cannot be read. That is, it is impossible to use the LDA instruction, memory operation instruction when the T flag is "1", addressing mode using direction register values as qualifiers, and bit test instructions such as BBC and BBS. It is also impossible to use bit operation instructions such as CLB and SEB and read/modify/write instructions of direction registers for calculations such as ROR. For setting direction registers, use the LDM instruction, STA instruction, etc. (5) A/D Conversion Do not execute the STP instruction during A/D conversion. (6) Instruction Execution Timing The instruction execution time can be obtained by multiplying the frequency of the internal clock by the number of cycles mentioned in the machine-language instruction table. The frequency of the internal clock is the same as that of the SOURCE in double-speed mode, twice the SOURCE cycle in high-speed mode, 4 times the SOURCE cycle in middle-speed mode and 8 times the SOURCE cycle in low-speed mode. (7) CPU Mode Register The processor mode bits can be written only once after releasing reset. Always set them to "002". After written, rewriting any data to these bits is disabled because they are locked. (Emulator MCU is excluded.) Also, the stack page bit (bit 2) is not locked. In order to prevent error-writing to the processor mode bits (at program runaway), write the CPU mode register at the start of the program that runs after releasing reset. (8) State transition Do not stop the clock selected as the operation clock because of setting of bits 0 to 2. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY NOTES ON HARDWARE (1) Handling of Power Source Pin In order to avoid a latch-up occurrence, connect a capacitor suitable for high frequencies as bypass capacitor between power source pin (VCC pin) and GND pin (VSS pin). A ceramic capacitor of 0.01 F to 0.1 F is recommended. Connect a capacitor across the power source pin and GND pin with the shortest possible wiring. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 53 of 70 7549 Group NOTES ON USE Countermeasures against noise It is necessary not only design the system taking measures against the noise as follows but to evaluate before actual use. 1. Shortest wiring length (1) Package Select the smallest possible package to make the total wiring length short. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (3) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. DIP SDIP SOP QFP Noise Fig 69. Selection of packages (2) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). XIN XOUT VSS XIN XOUT VSS N.G. Fig 71. Wiring for clock I/O pins O.K. Noise Reset circuit VSS RESET VSS (4) Wiring to CNVSS pin Connect CNVSS pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. In order to improve the noise reduction, to connect a 5 k resistor serially to the CNVSS pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. N.G. (Note) CNVSS The shortest Reset circuit VSS RESET VSS VSS About 5k (Note) The shortest O.K. Note: This indicates pin. Fig 70. Wiring for the RESET pin Fig 72. Wiring for the VPP pin of the QzPROM Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 54 of 70 7549 Group 2. Connection of bypass capacitor across VSS line and VCC line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY VCC VCC 3. Wiring to analog input pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 1000 pF capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. Noise VSS VSS (Note) N.G. O.K. Thermistor Microcomputer Analog input pin Fig 73. Bypass capacitor across the VSS line and the VCC line N.G. O.K. VSS Note : The resistor is used for dividing resistance with a thermistor. Fig 74. Analog signal line and a resistor and a capacitor * The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A/D conversion when the analog signal source of highimpedance is connected to an analog input pin. In order to obtain the A/D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 55 of 70 7549 Group 4. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY (3) Oscillator protection using VSS pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig 76. VSS pattern on the underside of an oscillator (1) Keeping oscillator away from large current signal lines Microcomputer Mutual inductance M Large current GND XIN XOUT VSS (2) Installing oscillator away from signal lines where potential levels change frequently N.G. Do not cross CNTR XIN XOUT VSS Fig 75. Wiring for a large current signal line/Writing of signal lines where potential levels change frequently Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 56 of 70 7549 Group 5. Setup for I/O ports Setup I/O ports using hardware and software as follows: Noise Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY O.K. Data bus Direction register Port latch I/O port pins Noise N.G. Fig 77. Setup for I/O ports 6. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. Main routine (SWDT) N CLI Main processing N (SWDT) =N? N Interrupt processing routine (SWDT) (SWDT)-1 Interrupt processing >0 RTI Return Main routine errors (SWDT) 0? 0 Interrupt processing routine errors Fig 78. Watchdog timer by software Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 57 of 70 7549 Group NOTES ON USE Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. Product shipped in blank As for the product shipped in blank, Renesas does not perform the writing test to user ROM area after the assembly process though the QzROM writing test is performed enough before the assembly process. Therefore, a writing error of approx.0.1 % may occur. Moreover, please note the contact of cables and foreign bodies on a socket, etc. because a writing environment may cause some writing errors. Overvoltage Take care not to apply the voltage above the Vcc pin voltage to other pins. Make sure that the voltage of the CNVSS pin (VPP power input pin for QzROM) does not change as shown in the bold-lined periods (Figure 79) when powering on and off. If the voltage changes as shown, the QzROM contents may be rewritten. (1) 1.8V VCC pin voltage (2) 1.8V Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Notes On ROM Code Protect (QzROM product shipped after writing) As for the QzROM product shipped after writing, the ROM code protect is specified according to the ROM option setup data in the mask file which is submitted at ordering. Renesas Technology corp. write the value of the ROM option setup data in the ROM code protect address (address FFDB16) when writing to the QzROM. As a result, in the contents of the ROM code protect address the ordered value may differ from the actual written value. The ROM option setup data in the mask file is "0016" for protect enabled or "FF16" for protect disabled. Therefore, the contents of the ROM code protect address (other than the user ROM area) of the QzROM product shipped after writing is "0016" or "FF16". Note that the mask file which has nothing at the ROM option data or has the data other than "0016" and "FF16" can not be accepted. DATA REQUIRED FOR QzROM WRITING ORDERS The following are necessary when ordering a QzROM product shipped after writing: 1. QzROM Writing Confirmation Form* 2. Mark Specification Form* 3. ROM data .......... Mask file * For the QzROM writing confirmation form and the mark specifi-cation form, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp). Note that we cannot deal with special font marking (customer's trademark etc.) in QzROM microcomputer. ~ ~ CNVSS pin voltage (1) The input voltage to other MCU pins rises before the VCC pin voltage rises. (2) The input voltage to other MCU pins falls before the VCC pin voltage falls. Note: If VCC falls below the minimum value 1.8 V (shaded areas), the internal circuit becomes unstable. Take additional care to prevent overvoltage. Fig 79. Timing Diagram (bold-lined periods are applicable) NOTES ON QzROM Notes On QzROM Writing Orders When ordering the QzROM product shipped after writing, submit the mask file (extension: .mask) which is made by the mask file converter MM. Be sure to set the ROM option ("MASK option" written in the mask file converter) setup when making the mask file by using the mask file converter MM. ~ ~ Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 58 of 70 7549 Group ELECTRICAL CHARACTERISTICS of 7549 Group Absolute Maximum Ratings Absolute maximum ratings Symbol VCC VI VI VI VO Pd Topr Tstg Parameter Power source voltage Input voltage P00-P07, P10-P17, P20, P21, P30, P31 ______ Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Conditions Ratings -0.3 to 6.5 Unit V V V V V mW C C Input voltage RESET Input voltage CNVSS Output voltage P00-P07, P10-P17, P20, P21, P30, P31 Power dissipation Operating temperature Storage temperature All voltages are based on VSS. When an input voltage is measured, output transistors are cut off. -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 Ta = 25 C 300 -20 to 85 -40 to 125 Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 59 of 70 7549 Group Recommended Operating Conditions Recommended operating conditions (1) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC Power source voltage High-speed on-chip oscillator Low-speed on-chip oscillator XIN oscillation, XCIN oscillation, external clock input Parameter Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Min. Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 0 0.8VCC 0.8VCC 0 0 0 VCC VCC 0.2VCC 0.2VCC 0.16VCC -60 60 60 -30 30 30 -10 10 30 -5 5 15 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 Unit Double-, high-, middle-, low-speed mode Double-, high-, middle-, low-speed mode Double-speed mode f(XIN) 8MHz f(XIN) 2MHz f(XIN) 1MHz High-, middle-, low-speed mode f(XIN) 8MHz f(XIN) 4MHz f(XIN) 1MHz 4.0 1.8 4.5 2.4 2.2 4.0 2.4 1.8 1.8 V V V V V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA XCIN oscillation VSS VIH VIH VIL VIL VIL IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOL(avg) IOL(avg) Power source voltage Double-, high-, middle-, low-speed mode f(XCIN) 50kHz "H" input voltage (Note 4) P00-P07, P10-P17, P21, P30, P31 "H" input voltage (Note 5) ______ RESET, XIN, XcIN "L" input voltage (Note 4) P00-P07, P10-P17, P21, P30, P31 "L" input voltage ______ RESET, CNVSS "L" input voltage (Note 5) XIN, XcIN "H" total peak output current (Notes 1, 4) P00-P07, P10-P17, P20, P21, P30, P31 "L" total peak output current (Note 1) P00-P07 "L" total peak output current (Notes 1, 4) P10-P17, P20, P21, P30, P31 "H" total average output current (Notes 1, 4) P00-P07, P10-P17, P20, P21, P30, P31 "L" total average output current (Note 1) P00-P07 "L" total average output current (Notes 1, 4) P10-P17, P20, P21, P30, P31 "H" peak output current (Notes 2, 4) P00-P07, P10-P17, P20, P21, P30, P31 "L" peak output current (Notes 2, 4) P00-P07 (drive capacity: weakness), P10-P17, P20, P21, P30, P31 "L" peak output current (Note 2) P00-P07 (drive capacity: strength) "H" average output current (Notes 3, 4) P00-P07, P10-P17, P20, P21, P30, P31 "L" average output current (Notes 3, 4) P00-P07 (drive capacity: weakness), P10-P17, P20, P21, P30, P31 "L" average output current (Notes 3) P00-P07 (drive capacity: strength) NOTES: 1. The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2. The peak output current is the peak current flowing in each port. 3. The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms. 4. P20 and P21 indicates these pins are used as I/O ports. 5. XIN and XCIN indicates these pins are used as clock pins. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 60 of 70 7549 Group Recommended operating conditions (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol f(XIN) Parameter Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Min. Typ. Max. 8 (Vcc - 2.4) x 2 +2 0.7 (Vcc - 2.2) +1 0.2 8 (Vcc - 2.4) +4 0.4 (Vcc - 1.8) +1 0.2 32.768 50 Unit MHz MHz MHz MHz MHz MHz kHz XIN oscillation frequency (Note 1) XIN oscillation External clock input Double-speed mode Vcc = 4.5-5.5 V Vcc = 2.4-4.5 V Vcc = 2.2-2.4 V High-, middle-, low-speed mode Vcc = 4.0-5.5 V Vcc = 2.4-4.0 V Vcc = 1.8-2.4 V XCIN oscillation frequency (Note 1) XCIN oscillation Double-, high-, middle-, low-speed mode Vcc = 1.8-5.5 V NOTE: 1. When the oscillation frequency has a duty cycle of 50 %. 8.0 Oscillation frequency: XIN(MHz) When XIN is used, the MCU can be operated within the range shown in diagonal lines. Confirm that the oscillation is stable within the operating supply voltage range before use. Contact the oscillator manufacturer for oscillation constants. XIN oscillation High-, middle-, low-speed mode XIN oscillation Double-speed mode 4.0 High-speed on-chip oscillator (5V/Typ:4MHz) Double-, high-, middle-, low-speed mode 2.0 1.0 Low-speed on-chip oscillator (5V/Typ:250kHz)/Double-, high-, middle-, low-speed mode / 0.0 0.0 1.5 XCIN oscillation/Double-, high-, middle-, low-speed mode / 2.0 3.0 2.5 3.5 Power source voltage: Vcc(V) 4.0 4.5 5.0 5.5 Fig 80. Power source voltage and oscillation frequency Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 61 of 70 7549 Group Electrical Characteristics Electrical characteristics (1) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Symbol VOH Parameter "H" output voltage (Notes 1, 3) P00-P07, P10-P17, P21, P30, P31 "L" output voltage (Note 1) P00-P07 (drive capacity: weakness) P10-P17, P21, P30, P31 Test conditions IOH = -5 mA, Vcc = 4.0-5.5 V IOH = -1.0 mA, Vcc = 1.8-5.5 V IOL = 5 mA, Vcc = 4.0-5.5 V IOL = 1.5 mA, Vcc = 4.0-5.5 V IOL = 1.0 mA, Vcc = 1.8-5.5 V VOL "L" output voltage P00-P07 (drive capacity: strength) IOL = 15 mA, Vcc = 4.0-5.5 V IOL = 1.5 mA, Vcc = 4.0-5.5 V IOL = 1.0 mA, Vcc = 1.8-5.5 V VT+ - VTHysteresis INT0, INT1, CAP0, P10-P17 (Note 4) RXD, SCLK, RESET VI = Vcc (Pin floating. Pull up transistors is disable) VI = Vcc VI = Vcc VI = Vcc VI = Vss (Pin floating. Pull up transistors is disable) VI = Vss VI = Vss VI = Vss VI = Vss (Pull up transistors is enable) VI = Vss When clock stopped Vcc = 4.0-5.5 V, Ta = 0-50 C Vcc = 4.0-5.5 V, Ta = -20-85 C Vcc = 5.0 V, Ta = 25 C Vcc = 5.0 V, Ta = 25 C 1.6 TBD TBD 125 62.5 4 4 250 150 -4.0 -0.3 -0.2 25 5.5 TBD MHz TBD 500 250 kHz kHz -0.5 4.0 0.5 -5.0 -0.7 0.5 Min. Vcc-1.5 Vcc-1.0 1.5 0.3 1.0 2.0 0.3 1.0 Typ. Max. Unit V V V V V V V V V VOL IIH IIH IIH IIH IIL IIL IIL IIL IIL RPH VRAM RHSOSC "H" input current (Note 1) P00-P07, P10-P17, P21, P30, P31 "H" input current "H" input current (Note 2) "H" input current (Note 2) RESET XIN XCIN 5.0 5 A A A A A mA A A mA k V "L" input current (Note 1) P00-P07, P10-P17, P21, P30, P31 "L" input current "L" input current (Note 2) "L" input current (Note 2) "L" input current Pull-up resistor value RAM hold voltage High-speed on-chip oscillator oscillation frequency Low-speed on-chip oscillator oscillation frequency Oscillation stop detection circuit detection frequency RESET XIN XCIN P00-P07, P10-P17 RESET RLSOSC DOSC NOTES: 1. 2. 3. 4. P20 and P21 indicates these pins are used as I/O ports. XIN and XCIN indicates these pins are used as clock pins. P05 is measured when the P05/TXD P-channel output disable bit of the UART1 control register (bit 4 of address 001B16) is "0". It is available only when operating key-on wake up. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 62 of 70 7549 Group Electrical characteristics (2) (VCC = 1.8 to 5.5V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Symbol Icc Parameter Power source current Test conditions High-speed on-chip oscillator: oscillation * Vcc = 5.0 V * Low-speed on-chip oscillator: stop * XIN: stop * Output transistors "off" * Low voltage detection circuit: enable Low-speed on-chip oscillator: oscillation * Vcc = 5.0 V * High-speed on-chip oscillator: stop * XIN: stop * Output transistors "off" * Low voltage detection circuit: enable f(XIN)=8 MHz (ceramic resonator) * Vcc = 5.0 V * High-speed on-chip oscillator: stop * Low-speed on-chip oscillator: stop * Output transistors "off" * Low voltage detection circuit: enable f(XCIN)=32.768 kHz * Vcc = 5.0 V * High-speed on-chip oscillator: stop * Low-speed on-chip oscillator: stop * Output transistors "off" * Low voltage detection circuit: enable Low-speed on-chip oscillator: oscillation * Vcc = 2.0 V * High-speed on-chip oscillator: stop * XIN: stop * Output transistors "off" * Low voltage detection circuit: enable f(XIN) = 2 MHz (ceramic resonator) * Vcc = 2.0 V * High-speed on-chip oscillator: stop * Low-speed on-chip oscillator: stop * Output transistors "off" * Low voltage detection circuit: enable f(XCIN) = 32.768 kHz * Vcc = 2.0 V * High-speed on-chip oscillator: stop * Low-speed on-chip oscillator: stop * Output transistors "off" * Low voltage detection circuit: enable Low voltage detection circuit self consumption current Double-speed mode Low-speed mode Wait mode, functions except timer 1 disabled Double-speed mode Low-speed mode Wait mode, functions except timer 1 disabled Double-speed mode Low-speed mode Wait mode, functions except timer 1 disabled Double-speed mode Low-speed mode Wait mode, functions except timer 1 disabled Low-speed mode Wait mode, functions except timer 1 disabled Low-speed mode Wait mode, functions except timer 1 disabled Low-speed mode Wait mode, functions except timer 1 disabled Ta = 25 C Vcc = 5.0 V Ta = 25 C Vcc = 2.0 V Increment when A/D conversion is executed f(XIN) = 8 MHz, Vcc = 5.0 V , Stop mode * Output transistors "off" * Low-speed on-chip oscillator: stop * Low voltage detection circuit: stop Ta = 25 C Ta = 85 C Min. Typ. 2.5 0.6 0.35 230 120 105 6.0 2.6 1.9 100 85 80 25 Max. 5.2 1.7 1.0 600 400 350 10 6.0 5.0 200 180 170 70 Unit mA mA mA A A A mA mA mA A A A A A A A A A A A mA 1.0 10 A A 23 60 190 450 150 430 24 65 23 70 20 0.5 0.1 55 Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 63 of 70 7549 Group A/D Converter Characteristics A/D Converter characteristics (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Symbol Parameter Resolution Absolute accuracy (excluding quantization error) tCONV RLADDER II(AD) Conversion time Ladder resistor A/D port input current Ta = -20-85 C, 2.7 Vcc 5.5V A/D conversion clock = f(SOURCE)/2 A/D conversion clock = f(SOURCE) 55 5.0 Test conditions Min. Typ. Max. 10 TBD 122 61 Unit bits LSB tc(SOURCE) tc(SOURCE) k A A/D Converter Recommended Operating Conditions (VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VCC Parameter Power source voltage Test conditions Ta = -20-85 C 4.0 Vcc 5.5 V 2.7 Vcc < 4.0 V Limits Min. 2.7 TBD TBD Typ. Max. 5.5 8 4 Unit V MHz MHz (AD) A/D conversion clock frequency (Note) NOTE: 1. When XCIN or the low-speed on-chip oscillator is selected as SOURCE, the A/D converter cannot be used. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 64 of 70 7549 Group Power-on reset circuit characteristics Power-on reset circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol VPOR TW(VPOR) TW(VPOR-VDET) Parameter Valid start voltage of power-on reset circuit (Note) VPOR hold time Rising time of valid power source of power-on reset circuit TW(VPOR) > 10s Test conditions Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Min. Typ. Max. 0 10 20 Unit V s ms NOTE: 1. VPOR is the start voltage level of Vcc for the built-in power-on reset circuit to operate normally. Keep VPOR to be lower than the Vcc voltage before rising of the Vcc power source to use the built-in power-on reset circuit. Set the built-in low voltage detection circuit to be valid when the built-in power-on reset is used. Low voltage detection circuit characteristics Low voltage detection circuit characteristics (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol Parameter Valid start voltage of low voltage detection circuit (Note) VLVD hold time Rising time of valid power source of low voltage detection circuit Detection voltage of low voltage detection circuit Detection voltage Hysteresis (when hysteresis is valid) Detection time of low 5voltage detection circuit TW(VLVD) > 10s Ta = 0-50 C Ta = -20-85 C Ta = -20-85 C 1.85 1.80 1.95 1.95 0.10 20 Test conditions Limits Min. 1.0 10 10 2.05 2.10 Typ. Max. Unit V s s V V V s VLVD TW(VLVD) TW(VLVD-VDET) VDETV(VDET+- VDET-) TDET NOTE: 1. VLVD is the start voltage level of Vcc for the built-in low voltage detection circuit to operate normally. If the Vcc power source becomes lower than VLVD, first set the Vcc voltage to be lower than VPOR. Next, according to the electrical characteristics of the power-on reset circuit, perform the rising of Vcc. VDET+ VDET- Note Vcc power source waveform VPOR VPOR 0V TW(VPOR)T Internal reset signal T(VPON-VDET) TDET TW(VLVD)T T(VLVD-VDET) Power-on reset circuit characteristics Low voltage detection circuit characteristics Note: If schmitt of the voltage drop detection circuit is set to be invalid, system is released from reset at the timing of rising to power source voltage VDET-. Fig 81. Electrical characteristics of power-on reset circuit and voltage drop detection circuit Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 65 of 70 7549 Group Timing Requirements Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ______ Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width INT0, INT1, CAP0 input "H" pulse width (Note 1) INT0, INT1, CAP0 input "L" pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input "H" pulse width (Note 2) Serial I/O clock input "L" pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Limits Min. 2 125 50 50 80 80 800 370 370 220 100 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) NOTES: 1. As for CAP0, it is the value when noise filter is not used. 2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ______ Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width INT0, INT1, CAP0 input "H" pulse width (Note 1) INT0, INT1, CAP0 input "L" pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input "H" pulse width (Note 2) Serial I/O clock input "L" pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Limits Min. 2 250 100 100 230 230 2000 950 950 400 200 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) NOTES: 1. As for CAP0, it is the value when noise filter is not used. 2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 66 of 70 7549 Group Timing requirements (3) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol ______ Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Parameter Reset input "L" pulse width External clock input cycle time External clock input "H" pulse width External clock input "L" pulse width INT0, INT1, CAP0 input "H" pulse width (Note 1) INT0, INT1, CAP0 input "L" pulse width (Note 1) Serial I/O clock input cycle time (Note 2) Serial I/O clock input "H" pulse width (Note 2) Serial I/O clock input "L" pulse width (Note 2) Serial I/O input set up time Serial I/O input hold time Limits Min. 2 500 200 200 460 460 4000 1900 1900 800 400 Typ. Max. Unit s ns ns ns ns ns ns ns ns ns ns tW(RESET) tC(XIN) tWH(XIN) tWL(XIN) tWH(INT0) tWL(INT0) tC(SCLK) tWH(SCLK) tWL(SCLK) tsu(RXD-SCLK) th(SCLK-RXD) NOTES: 1. As for CAP0, it is the value when noise filter is not used. 2. In this time, bit 6 of the serial I/O control register (address 001A16) is set to "1" (clock synchronous serial I/O is selected). When bit 6 of the serial I/O control register is "0" (clock asynchronous serial I/O is selected), the rating values are divided by 4. Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 67 of 70 7549 Group Switching Characteristics Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) -30 Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY Limits Min. tC(SCLK)/2-30 tC(SCLK)/2-30 140 Typ. Max. Unit ns ns ns ns 30 30 10 10 30 30 ns ns ns ns NOTE: 1. Pin XOUT is excluded. Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 20 20 -30 50 50 50 50 Limits Min. tC(SCLK)/2-50 tC(SCLK)/2-50 350 Typ. Max. Unit ns ns ns ns ns ns ns ns NOTE: 1. Pin XOUT is excluded. Switching characteristics (3) (VCC = 1.8 to 5.5 V, VSS = 0 V, Ta = -20 to 85 C, unless otherwise noted) Symbol tWH(SCLK) tWL(SCLK) td(SCLK-TXD) tV(SCLK-TXD) tr(SCLK) tf(SCLK) tr(CMOS) tf(CMOS) Parameter Serial I/O clock output "H" pulse width Serial I/O clock output "L" pulse width Serial I/O output delay time Serial I/O output valid time Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time (Note 1) CMOS output falling time (Note 1) 25 25 -30 70 70 70 70 Limits Min. tC(SCLK)/2-70 tC(SCLK)/2-70 450 Typ. Max. Unit ns ns ns ns ns ns ns ns NOTE: 1. Pin XOUT is excluded. Measured output pin 100pF CMOS output Fig 82. Switching characteristics measurement circuit diagram Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 68 of 70 7549 Group Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY tWH(INT0) tWL(INT0) 0.2VCC INT0, INT1 CAP0 0.8VCC tW(RESET) RESET 0.2VCC 0.8VCC tC(XIN) tWH(XIN) tWL(XIN) 0.2VCC XIN 0.8VCC tf tWL(SCLK) 0.2VCC tC(SCLK) tr 0.8VCC tWH(SCLK) SCLK tsu(RxD-SCLK) th(SCLK-RxD) RXD (at receive) td(SCLK-TxD) 0.8VCC 0.2VCC tv(SCLK-TxD) TXD (at transmit) Fig 83. Timing chart Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 69 of 70 7549 Group PACKAGE OUTLINE Notice: This is not a final specification. Some parametric limits are subject to change. PRELIMINARY JEITA Package Code P-SSOP24-5.3x10.1-0.80 RENESAS Code PRSP0024GA-A Previous Code 24P2Q-A MASS[Typ.] 0.2g 24 13 HE *1 E F NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET. 1 Index mark *2 12 c D A2 A1 Reference Symbol Dimension in Millimeters e *3 y bp D E A2 A A1 bp c HE e y L Detail F Min Nom Max 10.0 10.1 10.2 5.2 5.3 5.4 1.8 2.1 0.1 0.2 0 0.3 0.35 0.45 0.18 0.2 0.25 0 8 7.5 7.8 8.1 0.65 0.8 0.95 0.10 0.4 0.6 0.8 A Rev.2.00 Mar 05, 2007 REJ03B0202-0200 Page 70 of 70 L REVISION HISTORY Rev. 1.00 2.00 Date Page Dec 15, 2006 Feb 19, 2007 1 First edition issued 7549 Group Datasheet Description Summary FEATURES: "* LED output port" "* LED direct drive port" "* Built-in high-speed on-chip oscillator" "High-speed on-chip oscillator" "* Built-in low-speed on-chip oscillator" "Low-speed on-chip oscillator" *Power dissipation: "TBD" "30 mW" 4 6 Table 1: I/O port P00-P07; "LED direct drive ports" is added A/D converter; "8 channel" "x 8 channel" Table 2: P03 "Capture function pin" "Capture input pin" P10-P12 "Compare function pin" "Compare output pin" P13 "Timer 2 function pin" "Timer 2 output pin" P20, P21 "external oscillator pin" "clock pins" [CPU mode register]: Description is revised and moved from the page 12. Function set ROM Area: Description is revised and moved from the page 47. * Notes on A/D converter: (2) is added 10 11 12 14 15 16 17, 18 19 21 24 26 27 31 32 37, 38 38 39 40 42 43 44 Watchdog Timer is revised Fig 50, Fig 53 is revised * Notes on Watchdog Timer is revised Fig 56 is revised Clock Circuit is revised Oscillation Control is added Table 9 is added Fig 61 is revised Fig 62 is revised Fig 63 is revised "oscillation stop" "oscillation stop detection" Fig 64 is revised Fig 65 is revised, Note 4 is added * Notes on Function Set ROM Data 2 is deleted Table 10: P10 "ESDA input" "ESDA I/O", "Output" "I/O" 47 48 49 50 A-1 REVISION HISTORY Rev. 2.00 Date Page Feb 19, 2007 53 58 59 7549 Group Datasheet Description Summary (7) CPU Mode Register is revised Overvoltage: Description revised, Fig 79 is added ELECTRICAL CHARACTERISTICS is added A-2 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. 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Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. 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Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. 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